📄 spim.lis
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0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 ENDIF
0000 SPIM_MOSI_P15: EQU 0
0001 SPIM_MOSI_P16: EQU 1
0001 SPIM_MIS0_P15: EQU 1
0000 SPIM_MISO_P16: EQU 0
0000
0000 ;--------------------------------------------------
0000 ; Register constants and masks
0000 ;--------------------------------------------------
0080 SPIM_SWAP: EQU 0x80
0008 SPIM_SPIM_MODE_0: EQU 0x08 // MODE 0 - Leading edge latches data - pos clock
0000 SPIM_SPIM_MODE_1: EQU 0x00 // MODE 1 - Leading edge latches data - neg clock
000C SPIM_SPIM_MODE_2: EQU 0x0C // MODE 2 - Trailing edge latches data - pos clock
0008 SPIM_SPIM_MODE_3: EQU 0x08 // MODE 3 - Trailing edge latches data - neg clock
0040 SPIM_SPIM_LSB_FIRST: EQU 0x40 // LSB bit transmitted/received first
0000 SPIM_SPIM_MSB_FIRST: EQU 0x00 // MSB bit transmitted/received first
0000
0000 ;---------------------------
0000 ; SPIM Status register masks
0000 ;---------------------------
0000
0000 ;--------------------------------------------------
0000 ; Registers used by SPIM
0000 ;--------------------------------------------------
0000
0000 ; end of file SPIM.inc
0000
0000 ;-----------------------------------------------
0000 ; Global Symbols
0000 ;-----------------------------------------------
export SPIM_EnableInt
export _SPIM_EnableInt
export SPIM_DisableInt
export _SPIM_DisableInt
export SPIM_Start
export _SPIM_Start
export SPIM_Stop
export _SPIM_Stop
export SPIM_SetMOSI
export _SPIM_SetMOSI
export SPIM_SetMISO
export _SPIM_SetMISO
export SPIM_bIO
export _SPIM_bIO
;-----------------------------------------------
; Constant Definitions
;-----------------------------------------------
area UserModules (ROM, REL)
0000 .SECTION
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: SPIM_EnableInt
0000 ;
0000 ; DESCRIPTION:
0000 ; Enables this SPIM's interrupts by setting both the RX and TX interrupt
0000 ; masks.
0000 ;-----------------------------------------------------------------------------
0000 ;
0000 ; ARGUMENTS: none
0000 ;
0000 ; RETURNS: none
0000 ;
0000 ; SIDE EFFECTS:
0000 ; The A and X registers may be modified by this or future implementations
0000 ; of this function. The same is true for all RAM page pointer registers in
0000 ; the Large Memory Model. When necessary, it is the calling function's
0000 ; responsibility to perserve their values across calls to fastcall16
0000 ; functions.
0000 ;
0000 ; THEORY of OPERATION or PROCEDURE:
0000 ; Enables the SPI RX and TX interrupts
0000 ;-----------------------------------------------------------------------------
0000 SPIM_EnableInt:
0000 _SPIM_EnableInt:
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
0000 43E00C or reg[INT_MSK0], (INT_MSK0_SPI_RX | INT_MSK0_SPI_TX) ; enable specified interrupt enable bit
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_2 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_3 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
0003 7F RET
0004 .ENDSECTION
0004 .SECTION
0004 ;-----------------------------------------------------------------------------
0004 ; FUNCTION NAME: SPIM_DisableInt
0004 ;
0004 ; DESCRIPTION:
0004 ; Disables this SPIM's interrupt by clearing both the RX and TX interrupt
0004 ; masks.
0004 ;
0004 ;-----------------------------------------------------------------------------
0004 ;
0004 ; ARGUMENTS: none
0004 ;
0004 ; RETURNS: none
0004 ;
0004 ; SIDE EFFECTS:
0004 ; The A and X registers may be modified by this or future implementations
0004 ; of this function. The same is true for all RAM page pointer registers in
0004 ; the Large Memory Model. When necessary, it is the calling function's
0004 ; responsibility to perserve their values across calls to fastcall16
0004 ; functions.
0004 ;
0004 ; THEORY of OPERATION or PROCEDURE:
0004 ; Disables the SPI RX and TX interrupts
0004 ;-----------------------------------------------------------------------------
0004 SPIM_DisableInt:
0004 _SPIM_DisableInt:
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
0004 41E0F3 and reg[INT_MSK0], ~(INT_MSK0_SPI_RX | INT_MSK0_SPI_TX) ; disable specified interrupt enable bit
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_1 & RAM_USE_CLASS_2 )
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