digtalclk.fit.eqn

用Altera公司的QuartusII编写的电子钟程序

--ZB1L2 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result15w~45 at LC_X30_Y14_N6
--operation mode is normal

ZB1L2 = ZB1L1 & (C1_disp[0] # !J1_safe_q[16]) # !ZB1L1 & (J1_safe_q[16] & C1_disp[8]);


--C1_disp[5] is clock:inst1|disp[5] at LC_X26_Y15_N8
--operation mode is normal

C1_disp[5]_lut_out = C1L53 & (!C1_clk1s # !C1L093);
C1_disp[5] = DFFEAS(C1_disp[5]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L783, , , , );


--C1_disp[9] is clock:inst1|disp[9] at LC_X31_Y14_N4
--operation mode is normal

C1_disp[9]_lut_out = C1L73 & (!C1L093 # !C1_clk1s);
C1_disp[9] = DFFEAS(C1_disp[9]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L193, , , , );


--C1_disp[13] is clock:inst1|disp[13] at LC_X29_Y15_N8
--operation mode is normal

C1_disp[13]_lut_out = C1L93 & (!C1_clk1s # !C1L093);
C1_disp[13] = DFFEAS(C1_disp[13]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L104, , , , );


--ZB1L3 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result45w~44 at LC_X30_Y14_N2
--operation mode is normal

ZB1L3 = J1_safe_q[16] & (J1_safe_q[17] # C1_disp[9]) # !J1_safe_q[16] & C1_disp[13] & !J1_safe_q[17];


--C1_disp[1] is clock:inst1|disp[1] at LC_X27_Y13_N9
--operation mode is normal

C1_disp[1]_lut_out = C1L14 & (!C1L093 # !C1_clk1s);
C1_disp[1] = DFFEAS(C1_disp[1]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L183, , , , );


--ZB1L4 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result45w~45 at LC_X31_Y13_N6
--operation mode is normal

ZB1L4 = J1_safe_q[17] & (ZB1L3 & C1_disp[1] # !ZB1L3 & (C1_disp[5])) # !J1_safe_q[17] & (ZB1L3);


--C1_disp[10] is clock:inst1|disp[10] at LC_X31_Y15_N9
--operation mode is normal

C1_disp[10]_lut_out = C1L34 & (!C1_clk1s # !C1L093);
C1_disp[10] = DFFEAS(C1_disp[10]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L193, , , , );


--C1_disp[6] is clock:inst1|disp[6] at LC_X27_Y15_N4
--operation mode is normal

C1_disp[6]_lut_out = C1L54 & (!C1L093 # !C1_clk1s);
C1_disp[6] = DFFEAS(C1_disp[6]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L783, , , , );


--C1_disp[14] is clock:inst1|disp[14] at LC_X29_Y15_N9
--operation mode is normal

C1_disp[14]_lut_out = C1L64 & (!C1_clk1s # !C1L093);
C1_disp[14] = DFFEAS(C1_disp[14]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L104, , , , );


--ZB1L5 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result70w~44 at LC_X30_Y14_N7
--operation mode is normal

ZB1L5 = J1_safe_q[16] & (J1_safe_q[17]) # !J1_safe_q[16] & (J1_safe_q[17] & (C1_disp[6]) # !J1_safe_q[17] & C1_disp[14]);


--C1_disp[2] is clock:inst1|disp[2] at LC_X27_Y13_N1
--operation mode is normal

C1_disp[2]_lut_out = C1L84 & (!C1L093 # !C1_clk1s);
C1_disp[2] = DFFEAS(C1_disp[2]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L183, , , , );


--ZB1L6 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result70w~45 at LC_X31_Y13_N1
--operation mode is normal

ZB1L6 = J1_safe_q[16] & (ZB1L5 & C1_disp[2] # !ZB1L5 & (C1_disp[10])) # !J1_safe_q[16] & (ZB1L5);


--C1_disp[7] is clock:inst1|disp[7] at LC_X25_Y15_N6
--operation mode is normal

C1_disp[7]_lut_out = C1L05 & (!C1_clk1s # !C1L093);
C1_disp[7] = DFFEAS(C1_disp[7]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L783, , , , );


--C1_disp[11] is clock:inst1|disp[11] at LC_X29_Y13_N9
--operation mode is normal

C1_disp[11]_lut_out = C1L25 & (!C1L093 # !C1_clk1s);
C1_disp[11] = DFFEAS(C1_disp[11]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L193, , , , );


--C1_disp[15] is clock:inst1|disp[15] at LC_X23_Y15_N5
--operation mode is normal

C1_disp[15]_lut_out = !C1L35 & (U16L5 & U16L9 # !U16L5 & (C1L45));
C1_disp[15] = DFFEAS(C1_disp[15]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L104, , , , );


--ZB1L7 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result95w~44 at LC_X30_Y14_N4
--operation mode is normal

ZB1L7 = J1_safe_q[16] & (J1_safe_q[17] # C1_disp[11]) # !J1_safe_q[16] & C1_disp[15] & !J1_safe_q[17];


--C1_disp[3] is clock:inst1|disp[3] at LC_X26_Y13_N2
--operation mode is normal

C1_disp[3]_lut_out = C1L65 & (!C1L093 # !C1_clk1s);
C1_disp[3] = DFFEAS(C1_disp[3]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L183, , , , );


--ZB1L8 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result95w~45 at LC_X31_Y13_N8
--operation mode is normal

ZB1L8 = J1_safe_q[17] & (ZB1L7 & C1_disp[3] # !ZB1L7 & (C1_disp[7])) # !J1_safe_q[17] & (ZB1L7);


--G1L7 is bin2seg:inst9|data_out[6]~72 at LC_X31_Y13_N7
--operation mode is normal

G1L7 = ZB1L8 # ZB1L4 & (!ZB1L6 # !ZB1L2) # !ZB1L4 & (ZB1L6);


--G1L6 is bin2seg:inst9|data_out[5]~73 at LC_X31_Y13_N0
--operation mode is normal

G1L6 = ZB1L4 & !ZB1L8 & (ZB1L2 # !ZB1L6) # !ZB1L4 & (ZB1L8 & (ZB1L6) # !ZB1L8 & ZB1L2 & !ZB1L6);


--G1L5 is bin2seg:inst9|data_out[4]~74 at LC_X31_Y13_N2
--operation mode is normal

G1L5 = ZB1L4 & ZB1L2 & !ZB1L8 # !ZB1L4 & (ZB1L6 & (!ZB1L8) # !ZB1L6 & ZB1L2);


--G1L4 is bin2seg:inst9|data_out[3]~75 at LC_X31_Y13_N3
--operation mode is normal

G1L4 = ZB1L2 & (ZB1L4 $ (!ZB1L6)) # !ZB1L2 & (ZB1L4 & ZB1L8 & !ZB1L6 # !ZB1L4 & !ZB1L8 & ZB1L6);


--G1L3 is bin2seg:inst9|data_out[2]~76 at LC_X31_Y13_N4
--operation mode is normal

G1L3 = ZB1L8 & ZB1L6 & (ZB1L4 # !ZB1L2) # !ZB1L8 & ZB1L4 & !ZB1L2 & !ZB1L6;


--G1L2 is bin2seg:inst9|data_out[1]~77 at LC_X31_Y13_N5
--operation mode is normal

G1L2 = ZB1L4 & (ZB1L2 & ZB1L8 # !ZB1L2 & (ZB1L6)) # !ZB1L4 & ZB1L6 & (ZB1L2 $ ZB1L8);


--G1L1 is bin2seg:inst9|data_out[0]~78 at LC_X31_Y13_N9
--operation mode is normal

G1L1 = ZB1L6 & (ZB1L8 & !ZB1L4 # !ZB1L8 & (!ZB1L2)) # !ZB1L6 & ZB1L2 & (ZB1L4 $ !ZB1L8);


--C1L75 is clock:inst1|add~4111 at LC_X25_Y10_N9
--operation mode is normal

C1L75 = C1L78 $ !C1_alm_m[5];


--U52L3 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41 at LC_X26_Y9_N2
--operation mode is arithmetic

U52L3 = U52L8 $ (!EB4L9 & !EB4L01);

--U52L4 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~43 at LC_X26_Y9_N2
--operation mode is arithmetic

U52L4_cout_0 = !U52L8 & (EB4L9 # EB4L01);
U52L4 = CARRY(U52L4_cout_0);

--U52L5 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~43COUT1_71 at LC_X26_Y9_N2
--operation mode is arithmetic

U52L5_cout_1 = !U52L9 & (EB4L9 # EB4L01);
U52L5 = CARRY(U52L5_cout_1);


--T01L3 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32 at LC_X25_Y9_N3
--operation mode is normal

T01L3 = T01L5;


--U42L3 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41 at LC_X27_Y9_N4
--operation mode is normal

U42L3 = !U42L8;


--EB4L01 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~467 at LC_X25_Y9_N9
--operation mode is normal

EB4L01 = !U42L3 & (C1_alm_m[3] $ T01L3);


--U42L4 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~46 at LC_X27_Y9_N1
--operation mode is arithmetic

U42L4 = U42L11 $ (!EB4L1 & !EB4L2);

--U42L5 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48 at LC_X27_Y9_N1
--operation mode is arithmetic

U42L5_cout_0 = !EB4L1 & !EB4L2 & !U42L11;
U42L5 = CARRY(U42L5_cout_0);

--U42L6 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48COUT1 at LC_X27_Y9_N1
--operation mode is arithmetic

U42L6_cout_1 = !EB4L1 & !EB4L2 & !U42L21;
U42L6 = CARRY(U42L6_cout_1);


--EB4L9 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~17 at LC_X27_Y9_N8
--operation mode is normal

EB4L9 = U42L3 & U42L4;


--U52L6 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~46 at LC_X26_Y9_N4
--operation mode is normal

U52L6 = !U52L11;


--EB4L51 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[28]~468 at LC_X26_Y9_N6
--operation mode is normal

EB4L51 = U52L6 & U52L3 # !U52L6 & (EB4L01 # EB4L9);


--U52L7 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51 at LC_X26_Y9_N1
--operation mode is arithmetic

U52L7 = U52L41 $ (!EB4L8 & !EB4L7);

--U52L8 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53 at LC_X26_Y9_N1
--operation mode is arithmetic

U52L8_cout_0 = !EB4L8 & !EB4L7 & !U52L41;
U52L8 = CARRY(U52L8_cout_0);

--U52L9 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53COUT1 at LC_X26_Y9_N1
--operation mode is arithmetic

U52L9_cout_1 = !EB4L8 & !EB4L7 & !U52L51;
U52L9 = CARRY(U52L9_cout_1);


--EB4L41 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[27]~469 at LC_X26_Y9_N8
--operation mode is normal

EB4L41 = U52L6 & U52L7 # !U52L6 & (U42L3 $ C1_alm_m[2]);


--C1L85 is clock:inst1|add~4116 at LC_X26_Y9_N9
--operation mode is normal

C1L85 = EB4L41 & (C1_alm_m[1] $ U52L6);


--C1L95 is clock:inst1|add~4117 at LC_X24_Y10_N4
--operation mode is normal

C1L95 = C1L09 $ C1_alm_m[5];


--C1_pos[0] is clock:inst1|pos[0] at LC_X25_Y13_N8
--operation mode is normal

C1_pos[0]_lut_out = !C1L441;
C1_pos[0] = DFFEAS(C1_pos[0]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L093, , , , );


--C1_num is clock:inst1|num at LC_X25_Y13_N1
--operation mode is normal

C1_num_lut_out = D3_keyout & C1L184 & (C1_num) # !D3_keyout & (C1_lastkey3 # C1L184 & C1_num);
C1_num = DFFEAS(C1_num_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L093, , , , );


--C1L633 is clock:inst1|alm_m[1]~1249 at LC_X24_Y11_N6
--operation mode is normal

C1L633 = C1_pos[0] & !C1_num;


--C1L06 is clock:inst1|add~4122 at LC_X26_Y11_N6
--operation mode is normal

C1L06_carry_eqn = (!C1L802 & C1L39) # (C1L802 & C1L49);
C1L06 = C1L06_carry_eqn $ !C1_alm_m[5];


--C1L16 is clock:inst1|add~4127 at LC_X25_Y12_N6
--operation mode is normal

C1L16_carry_eqn = (!C1L212 & C1L69) # (C1L212 & C1L79);
C1L16 = C1L16_carry_eqn $ C1_alm_m[5];


--C1L3 is clock:inst1|LessThan~1386 at LC_X25_Y12_N0
--operation mode is normal

C1L3 = !C1_alm_m[3] & (!C1_alm_m[1] & !C1_alm_m[2]);


--C1L4 is clock:inst1|LessThan~1387 at LC_X27_Y10_N0
--operation mode is normal

C1L4 = !C1_alm_m[5] & (!C1_alm_m[4]);


--C1L643 is clock:inst1|alm_m[5]~1250 at LC_X25_Y11_N3
--operation mode is normal

C1L643 = C1_num # C1L52 & !C1_pos[0];


--C1L5 is clock:inst1|LessThan~1388 at LC_X26_Y10_N0
--operation mode is normal

C1L5 = C1_alm_m[3] & (C1_alm_m[2] # C1_alm_m[1]) # !C1L4;


--C1L743 is clock:inst1|alm_m[5]~1251 at LC_X24_Y10_N6
--operation mode is normal

C1L743 = C1_num # C1_pos[0] & C1L5;


--C1L053 is clock:inst1|alm_m~1252 at LC_X25_Y11_N4
--operation mode is normal

C1L053 = C1L743 & (C1L16 & C1L643) # !C1L743 & (C1L06 # !C1L643);


--C1L153 is clock:inst1|alm_m~1253 at LC_X25_Y11_N1
--operation mode is normal

C1L153 = C1L633 & (C1L053 & (!C1L003) # !C1L053 & C1L95) # !C1L633 & C1L053;


--C1L733 is clock:inst1|alm_m[1]~1254 at LC_X24_Y10_N9
--operation mode is normal

C1L733 = C1_pos[0] & (C1_num);


--C1L6 is clock:inst1|LessThan~1389 at LC_X25_Y12_N9
--operation mode is normal

C1L6 = C1_alm_m[2] # C1_alm_m[0] & C1_alm_m[1];


--C1L7 is clock:inst1|LessThan~1390 at LC_X24_Y12_N4
--operation mode is normal

C1L7 = C1_alm_m[5] & C1_alm_m[4] & C1_alm_m[3] & C1L6;


--C1L843 is clock:inst1|alm_m[5]~1255 at LC_X25_Y11_N8
--operation mode is normal

C1L843 = !C1_pos[0] & C1L7 & C1_num;


--C1L8 is clock:inst1|LessThan~1391 at LC_X25_Y11_N9
--operation mode is normal

C1L8 = C1_alm_m[5] & C1_alm_m[4];


--C1L943 is clock:inst1|alm_m[5]~1256 at LC_X25_Y11_N0
--operation mode is normal

C1L943 = C1L843 # C1L8 & C1L733 & !C1L3;


--J1_modulus_trigger is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|modulus_trigger at LC_X8_Y13_N9
--operation mode is normal

J1_modulus_trigger_carry_eqn = (!J1L94 & J1L06) # (J1L94 & J1L16);
J1_modulus_trigger = J1_modulus_trigger_carry_eqn # J1L1;


--C1L543 is clock:inst1|alm_m[5]~42 at LC_X28_Y13_N8
--operation mode is normal

C1L543 = !C1_pos[1] & C1_lastas & (!C1_alm_set);


--U82L3 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~43 at LC_X29_Y11_N7
--operation mode is arithmetic