digtalclk.fit.eqn

用Altera公司的QuartusII编写的电子钟程序

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--C1_alm_m[5] is clock:inst1|alm_m[5] at LC_X25_Y11_N2
--operation mode is normal

C1_alm_m[5]_lut_out = !C1L943 & (C1L733 & C1L75 # !C1L733 & (C1L153));
C1_alm_m[5] = DFFEAS(C1_alm_m[5]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , , );


--C1_alm_h[3] is clock:inst1|alm_h[3] at LC_X26_Y12_N7
--operation mode is normal

C1_alm_h[3]_lut_out = C1L313 & (C1L633 & C1L613 # !C1L633 & (C1L813));
C1_alm_h[3] = DFFEAS(C1_alm_h[3]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L513, , , , );


--A1L8 is inst2~78 at LC_X24_Y12_N6
--operation mode is normal

A1L8 = C1_alm_m[5] & C1_m[5] & (C1_alm_h[3] $ !C1_h[3]) # !C1_alm_m[5] & !C1_m[5] & (C1_alm_h[3] $ !C1_h[3]);


--C1_alm_m[1] is clock:inst1|alm_m[1] at LC_X26_Y10_N5
--operation mode is arithmetic

C1_alm_m[1]_lut_out = C1L663;
C1_alm_m[1] = DFFEAS(C1_alm_m[1]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , !C1L933, );

--U52L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT at LC_X26_Y10_N5
--operation mode is arithmetic

U52L1_cout_0 = C1_alm_m[1];
U52L1 = CARRY(U52L1_cout_0);

--U52L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUTCOUT1 at LC_X26_Y10_N5
--operation mode is arithmetic

U52L2_cout_1 = C1_alm_m[1];
U52L2 = CARRY(U52L2_cout_1);


--C1_m[1] is clock:inst1|m[1] at LC_X16_Y12_N0
--operation mode is arithmetic

C1_m[1]_lut_out = C1L851;
C1_m[1] = DFFEAS(C1_m[1]_lut_out, GLOBAL(C1_clk1m), VCC, , , C1L664, !GLOBAL(C1_set), , );

--U72L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT at LC_X16_Y12_N0
--operation mode is arithmetic

U72L1_cout_0 = C1_m[1];
U72L1 = CARRY(U72L1_cout_0);

--U72L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUTCOUT1 at LC_X16_Y12_N0
--operation mode is arithmetic

U72L2_cout_1 = C1_m[1];
U72L2 = CARRY(U72L2_cout_1);


--C1_alm_m[4] is clock:inst1|alm_m[4] at LC_X25_Y10_N3
--operation mode is normal

C1_alm_m[4]_lut_out = !C1L943 & (C1L733 & (C1L68) # !C1L733 & C1L353);
C1_alm_m[4] = DFFEAS(C1_alm_m[4]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , , );


--C1L494 is clock:inst1|spk~4 at LC_X24_Y12_N8
--operation mode is normal

C1L494 = C1_m[4] $ (C1_alm_m[4]);


--A1L9 is inst2~79 at LC_X24_Y12_N3
--operation mode is normal

A1L9 = !C1L494 & A1L8 & (C1_m[1] $ !C1_alm_m[1]);


--C1_alm_m[3] is clock:inst1|alm_m[3] at LC_X26_Y10_N1
--operation mode is arithmetic

C1_alm_m[3]_lut_out = C1L763;
C1_alm_m[3] = DFFEAS(C1_alm_m[3]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , !C1L933, );

--T01L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT at LC_X26_Y10_N1
--operation mode is arithmetic

T01L1_cout_0 = C1_alm_m[3];
T01L1 = CARRY(T01L1_cout_0);

--T01L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUTCOUT1 at LC_X26_Y10_N1
--operation mode is arithmetic

T01L2_cout_1 = C1_alm_m[3];
T01L2 = CARRY(T01L2_cout_1);


--C1_alm_h[0] is clock:inst1|alm_h[0] at LC_X28_Y12_N3
--operation mode is normal

C1_alm_h[0]_lut_out = C1_pos[0] & C1_alm_h[0] # !C1_pos[0] & (C1L023);
C1_alm_h[0] = DFFEAS(C1_alm_h[0]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L513, , , , );


--C1_m[3] is clock:inst1|m[3] at LC_X18_Y14_N1
--operation mode is arithmetic

C1_m[3]_lut_out = C1L361;
C1_m[3] = DFFEAS(C1_m[3]_lut_out, GLOBAL(C1_clk1m), VCC, , , C1L074, !GLOBAL(C1_set), , );

--T11L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT at LC_X18_Y14_N1
--operation mode is arithmetic

T11L1_cout_0 = C1_m[3];
T11L1 = CARRY(T11L1_cout_0);

--T11L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUTCOUT1 at LC_X18_Y14_N1
--operation mode is arithmetic

T11L2_cout_1 = C1_m[3];
T11L2 = CARRY(T11L2_cout_1);


--A1L01 is inst2~80 at LC_X24_Y12_N7
--operation mode is normal

A1L01 = C1_alm_h[0] & C1_h[0] & (C1_alm_m[3] $ !C1_m[3]) # !C1_alm_h[0] & !C1_h[0] & (C1_alm_m[3] $ !C1_m[3]);


--C1_alm_h[1] is clock:inst1|alm_h[1] at LC_X29_Y12_N1
--operation mode is arithmetic

C1_alm_h[1]_lut_out = C1L723;
C1_alm_h[1] = DFFEAS(C1_alm_h[1]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L513, , , !C1L313, );

--U82L1 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT at LC_X29_Y12_N1
--operation mode is arithmetic

U82L1_cout_0 = C1_alm_h[1];
U82L1 = CARRY(U82L1_cout_0);

--U82L2 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUTCOUT1 at LC_X29_Y12_N1
--operation mode is arithmetic

U82L2_cout_1 = C1_alm_h[1];
U82L2 = CARRY(U82L2_cout_1);


--C1_alm_m[0] is clock:inst1|alm_m[0] at LC_X24_Y11_N5
--operation mode is normal

C1_alm_m[0]_lut_out = C1_pos[0] & C1_alm_m[0] # !C1_pos[0] & (C1L653);
C1_alm_m[0] = DFFEAS(C1_alm_m[0]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , , );


--C1_h[1] is clock:inst1|h[1] at LC_X22_Y12_N6
--operation mode is arithmetic

C1_h[1]_lut_out = C1L822;
C1_h[1] = DFFEAS(C1_h[1]_lut_out, GLOBAL(C1_clk1h), VCC, , , C1L034, !GLOBAL(C1_set), , );

--U92L1 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT at LC_X22_Y12_N6
--operation mode is arithmetic

U92L1_cout_0 = C1_h[1];
U92L1 = CARRY(U92L1_cout_0);

--U92L2 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUTCOUT1 at LC_X22_Y12_N6
--operation mode is arithmetic

U92L2_cout_1 = C1_h[1];
U92L2 = CARRY(U92L2_cout_1);


--A1L11 is inst2~81 at LC_X24_Y12_N0
--operation mode is normal

A1L11 = C1_h[1] & C1_alm_h[1] & (C1_m[0] $ !C1_alm_m[0]) # !C1_h[1] & !C1_alm_h[1] & (C1_m[0] $ !C1_alm_m[0]);


--J1_safe_q[15] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[15] at LC_X8_Y13_N5
--operation mode is arithmetic

J1_safe_q[15]_carry_eqn = J1L94;
J1_safe_q[15]_lut_out = J1_safe_q[15] $ J1_safe_q[15]_carry_eqn;
J1_safe_q[15] = DFFEAS(J1_safe_q[15]_lut_out, GLOBAL(clk50mhz), VCC, , , ~GND, , , J1_modulus_trigger);

--J1L15 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella15~COUT at LC_X8_Y13_N5
--operation mode is arithmetic

J1L15_cout_0 = !J1L94 # !J1_safe_q[15];
J1L15 = CARRY(J1L15_cout_0);

--J1L25 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella15~COUTCOUT1_2 at LC_X8_Y13_N5
--operation mode is arithmetic

J1L25_cout_1 = !J1L94 # !J1_safe_q[15];
J1L25 = CARRY(J1L25_cout_1);


--C1_alm_h[4] is clock:inst1|alm_h[4] at LC_X26_Y12_N4
--operation mode is normal

C1_alm_h[4]_lut_out = C1L423 & (C1L223 $ (C1_pos[0])) # !C1L423 & C1L223 & (C1L323 # !C1_pos[0]);
C1_alm_h[4] = DFFEAS(C1_alm_h[4]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L513, , , , );


--C1_alm_h[2] is clock:inst1|alm_h[2] at LC_X29_Y12_N8
--operation mode is arithmetic

C1_alm_h[2]_lut_out = C1L233;
C1_alm_h[2] = DFFEAS(C1_alm_h[2]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L513, , , !C1L313, );

--T21L1 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT at LC_X29_Y12_N8
--operation mode is arithmetic

T21L1_cout_0 = C1_alm_h[2];
T21L1 = CARRY(T21L1_cout_0);

--T21L2 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUTCOUT1 at LC_X29_Y12_N8
--operation mode is arithmetic

T21L2_cout_1 = C1_alm_h[2];
T21L2 = CARRY(T21L2_cout_1);


--C1_h[2] is clock:inst1|h[2] at LC_X21_Y12_N6
--operation mode is arithmetic

C1_h[2]_lut_out = C1L232;
C1_h[2] = DFFEAS(C1_h[2]_lut_out, GLOBAL(C1_clk1h), VCC, , , C1L434, !GLOBAL(C1_set), , );

--T31L1 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT at LC_X21_Y12_N6
--operation mode is arithmetic

T31L1_cout_0 = C1_h[2];
T31L1 = CARRY(T31L1_cout_0);

--T31L2 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUTCOUT1 at LC_X21_Y12_N6
--operation mode is arithmetic

T31L2_cout_1 = C1_h[2];
T31L2 = CARRY(T31L2_cout_1);


--A1L21 is inst2~82 at LC_X26_Y12_N0
--operation mode is normal

A1L21 = C1_h[4] & C1_alm_h[4] & (C1_h[2] $ !C1_alm_h[2]) # !C1_h[4] & !C1_alm_h[4] & (C1_h[2] $ !C1_alm_h[2]);


--C1_alm_m[2] is clock:inst1|alm_m[2] at LC_X26_Y10_N7
--operation mode is arithmetic

C1_alm_m[2]_lut_out = C1L863;
C1_alm_m[2] = DFFEAS(C1_alm_m[2]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L543, , , !C1L933, );

--U42L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT at LC_X26_Y10_N7
--operation mode is arithmetic

U42L1_cout_0 = C1_alm_m[2];
U42L1 = CARRY(U42L1_cout_0);

--U42L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUTCOUT1 at LC_X26_Y10_N7
--operation mode is arithmetic

U42L2_cout_1 = C1_alm_m[2];
U42L2 = CARRY(U42L2_cout_1);


--C1_m[2] is clock:inst1|m[2] at LC_X18_Y13_N1
--operation mode is arithmetic

C1_m[2]_lut_out = C1L761;
C1_m[2] = DFFEAS(C1_m[2]_lut_out, GLOBAL(C1_clk1m), VCC, , , C1L474, !GLOBAL(C1_set), , );

--U62L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT at LC_X18_Y13_N1
--operation mode is arithmetic

U62L1_cout_0 = C1_m[2];
U62L1 = CARRY(U62L1_cout_0);

--U62L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUTCOUT1 at LC_X18_Y13_N1
--operation mode is arithmetic

U62L2_cout_1 = C1_m[2];
U62L2 = CARRY(U62L2_cout_1);


--A1L31 is inst2~83 at LC_X26_Y12_N9
--operation mode is normal

A1L31 = J1_safe_q[15] & A1L21 & (C1_alm_m[2] $ !C1_m[2]);


--inst2 is inst2 at LC_X24_Y12_N2
--operation mode is normal

inst2 = A1L01 & A1L11 & A1L31 & A1L9;


--J1_safe_q[16] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[16] at LC_X8_Y13_N6
--operation mode is arithmetic

J1_safe_q[16]_carry_eqn = (!J1L94 & J1L15) # (J1L94 & J1L25);
J1_safe_q[16]_lut_out = J1_safe_q[16] $ (!J1_safe_q[16]_carry_eqn);
J1_safe_q[16] = DFFEAS(J1_safe_q[16]_lut_out, GLOBAL(clk50mhz), VCC, , , ~GND, , , J1_modulus_trigger);

--J1L45 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella16~COUT at LC_X8_Y13_N6
--operation mode is arithmetic

J1L45_cout_0 = J1_safe_q[16] & (!J1L15);
J1L45 = CARRY(J1L45_cout_0);

--J1L55 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella16~COUTCOUT1_9 at LC_X8_Y13_N6
--operation mode is arithmetic

J1L55_cout_1 = J1_safe_q[16] & (!J1L25);
J1L55 = CARRY(J1L55_cout_1);


--J1_safe_q[17] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[17] at LC_X8_Y13_N7
--operation mode is arithmetic

J1_safe_q[17]_carry_eqn = (!J1L94 & J1L45) # (J1L94 & J1L55);
J1_safe_q[17]_lut_out = J1_safe_q[17] $ (J1_safe_q[17]_carry_eqn);
J1_safe_q[17] = DFFEAS(J1_safe_q[17]_lut_out, GLOBAL(clk50mhz), VCC, , , ~GND, , , J1_modulus_trigger);

--J1L75 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella17~COUT at LC_X8_Y13_N7
--operation mode is arithmetic

J1L75_cout_0 = !J1L45 # !J1_safe_q[17];
J1L75 = CARRY(J1L75_cout_0);

--J1L85 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella17~COUTCOUT1_9 at LC_X8_Y13_N7
--operation mode is arithmetic

J1L85_cout_1 = !J1L55 # !J1_safe_q[17];
J1L85 = CARRY(J1L85_cout_1);


--J1L2 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|cmpr1_aeb_int~137 at LC_X9_Y13_N2
--operation mode is normal

J1L2 = J1_safe_q[17] & (J1_safe_q[16]);


--BC1L3 is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode24w[2]~34 at LC_X9_Y13_N8
--operation mode is normal

BC1L3 = !J1_safe_q[16] & (J1_safe_q[17]);


--BC1L4 is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode24w[2]~35 at LC_X9_Y13_N7
--operation mode is normal

BC1L4 = J1_safe_q[16] & (!J1_safe_q[17]);


--BC1_w_anode1w[2] is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode1w[2] at LC_X9_Y13_N1
--operation mode is normal

BC1_w_anode1w[2] = J1_safe_q[16] # J1_safe_q[17];


--C1_disp[8] is clock:inst1|disp[8] at LC_X29_Y13_N2
--operation mode is normal

C1_disp[8]_lut_out = C1L72 & (!C1_clk1s # !C1L093);
C1_disp[8] = DFFEAS(C1_disp[8]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L193, , , , );


--C1_disp[4] is clock:inst1|disp[4] at LC_X29_Y14_N0
--operation mode is normal

C1_disp[4]_lut_out = C1L92 & (!C1L093 # !C1_clk1s);
C1_disp[4] = DFFEAS(C1_disp[4]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L783, , , , );


--C1_disp[12] is clock:inst1|disp[12] at LC_X29_Y15_N4
--operation mode is normal

C1_disp[12]_lut_out = C1L13 & (!C1_clk1s # !C1L093);
C1_disp[12] = DFFEAS(C1_disp[12]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L104, , , , );


--ZB1L1 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result15w~44 at LC_X30_Y14_N5
--operation mode is normal

ZB1L1 = J1_safe_q[16] & (J1_safe_q[17]) # !J1_safe_q[16] & (J1_safe_q[17] & C1_disp[4] # !J1_safe_q[17] & (C1_disp[12]));


--C1_disp[0] is clock:inst1|disp[0] at LC_X27_Y13_N8
--operation mode is normal

C1_disp[0]_lut_out = C1L33 & (!C1L093 # !C1_clk1s);
C1_disp[0] = DFFEAS(C1_disp[0]_lut_out, GLOBAL(J1_modulus_trigger), VCC, , C1L183, , , , );