digtalclk.map.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_me8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_me8 " "Info: Found entity 1: add_sub_me8" {  } { { "db/add_sub_me8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_me8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ne8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ne8 " "Info: Found entity 1: add_sub_ne8" {  } { { "db/add_sub_ne8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_ne8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oe8 " "Info: Found entity 1: add_sub_oe8" {  } { { "db/add_sub_oe8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_oe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ma8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ma8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ma8 " "Info: Found entity 1: add_sub_ma8" {  } { { "db/add_sub_ma8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_ma8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_kdf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_kdf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_kdf " "Info: Found entity 1: lpm_divide_kdf" {  } { { "db/lpm_divide_kdf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_kdf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_jhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_jhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_jhg " "Info: Found entity 1: sign_div_unsign_jhg" {  } { { "db/sign_div_unsign_jhg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_jhg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_bld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_bld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_bld " "Info: Found entity 1: alt_u_div_bld" {  } { { "db/alt_u_div_bld.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_bld.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_4nf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_4nf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_4nf " "Info: Found entity 1: lpm_divide_4nf" {  } { { "db/lpm_divide_4nf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_4nf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_6jg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_6jg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_6jg " "Info: Found entity 1: sign_div_unsign_6jg" {  } { { "db/sign_div_unsign_6jg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_6jg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_hod.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_hod.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_hod " "Info: Found entity 1: alt_u_div_hod" {  } { { "db/alt_u_div_hod.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_hod.tdf" 38 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_re8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_re8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_re8 " "Info: Found entity 1: add_sub_re8" {  } { { "db/add_sub_re8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_re8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pe8 " "Info: Found entity 1: add_sub_pe8" {  } { { "db/add_sub_pe8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_pe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qe8 " "Info: Found entity 1: add_sub_qe8" {  } { { "db/add_sub_qe8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_qe8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pa8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pa8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pa8 " "Info: Found entity 1: add_sub_pa8" {  } { { "db/add_sub_pa8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_pa8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_4ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_4ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_4ff " "Info: Found entity 1: lpm_divide_4ff" {  } { { "db/lpm_divide_4ff.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_4ff.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_3jg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_3jg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_3jg " "Info: Found entity 1: sign_div_unsign_3jg" {  } { { "db/sign_div_unsign_3jg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_3jg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_bod.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_bod.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_bod " "Info: Found entity 1: alt_u_div_bod" {  } { { "db/alt_u_div_bod.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_bod.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_jlf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_jlf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_jlf " "Info: Found entity 1: lpm_divide_jlf" {  } { { "db/lpm_divide_jlf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_jlf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_lhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_lhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_lhg " "Info: Found entity 1: sign_div_unsign_lhg" {  } { { "db/sign_div_unsign_lhg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_lhg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_fld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_fld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_fld " "Info: Found entity 1: alt_u_div_fld" {  } { { "db/alt_u_div_fld.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_fld.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ilf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ilf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ilf " "Info: Found entity 1: lpm_divide_ilf" {  } { { "db/lpm_divide_ilf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_ilf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_1nf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_1nf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_1nf " "Info: Found entity 1: lpm_divide_1nf" {  } { { "db/lpm_divide_1nf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_1nf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hlf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_hlf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hlf " "Info: Found entity 1: lpm_divide_hlf" {  } { { "db/lpm_divide_hlf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_hlf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_eof.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_eof.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_eof " "Info: Found entity 1: lpm_divide_eof" {  } { { "db/lpm_divide_eof.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_eof.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_gkg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_gkg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_gkg " "Info: Found entity 1: sign_div_unsign_gkg" {  } { { "db/sign_div_unsign_gkg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_gkg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_5rd.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_5rd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_5rd " "Info: Found entity 1: alt_u_div_5rd" {  } { { "db/alt_u_div_5rd.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_5rd.tdf" 44 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5g8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5g8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5g8 " "Info: Found entity 1: add_sub_5g8" {  } { { "db/add_sub_5g8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_5g8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_se8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_se8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_se8 " "Info: Found entity 1: add_sub_se8" {  } { { "db/add_sub_se8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_se8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4g8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4g8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4g8 " "Info: Found entity 1: add_sub_4g8" {  } { { "db/add_sub_4g8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_4g8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3c8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3c8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3c8 " "Info: Found entity 1: add_sub_3c8" {  } { { "db/add_sub_3c8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_3c8.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_mdf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_mdf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_mdf " "Info: Found entity 1: lpm_divide_mdf" {  } { { "db/lpm_divide_mdf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_mdf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "1558 " "Info: Implemented 1558 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "1541 " "Info: Implemented 1541 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 117 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 117 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 29 21:15:36 2007 " "Info: Processing ended: Mon Oct 29 21:15:36 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0}  } {  } 0}