digtalclk.map.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(293) " "Warning: Verilog HDL assignment warning at clock.v(293): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 293 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(295) " "Warning: Verilog HDL assignment warning at clock.v(295): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 295 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(298) " "Warning: Verilog HDL assignment warning at clock.v(298): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 298 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(300) " "Warning: Verilog HDL assignment warning at clock.v(300): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 300 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(307) " "Warning: Verilog HDL assignment warning at clock.v(307): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 307 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(309) " "Warning: Verilog HDL assignment warning at clock.v(309): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 309 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(312) " "Warning: Verilog HDL assignment warning at clock.v(312): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 312 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(314) " "Warning: Verilog HDL assignment warning at clock.v(314): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 314 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(318) " "Warning: Verilog HDL assignment warning at clock.v(318): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 318 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(320) " "Warning: Verilog HDL assignment warning at clock.v(320): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 320 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(323) " "Warning: Verilog HDL assignment warning at clock.v(323): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 323 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(325) " "Warning: Verilog HDL assignment warning at clock.v(325): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 325 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_counter0.v 1 1 " "Info: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter0 " "Info: Found entity 1: lpm_counter0" {  } { { "lpm_counter0.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_counter0.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter0 lpm_counter0:inst " "Info: Elaborating entity \"lpm_counter0\" for hierarchy \"lpm_counter0:inst\"" {  } { { "digtalclk.bdf" "inst" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 40 136 280 136 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter lpm_counter0:inst\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\"" {  } { { "lpm_counter0.v" "lpm_counter_component" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_counter0.v" 69 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_gu8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_gu8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_gu8 " "Info: Found entity 1: cntr_gu8" {  } { { "db/cntr_gu8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/cntr_gu8.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_gu8 lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated " "Info: Elaborating entity \"cntr_gu8\" for hierarchy \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 251 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "skey skey:inst3 " "Info: Elaborating entity \"skey\" for hierarchy \"skey:inst3\"" {  } { { "digtalclk.bdf" "inst3" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 144 136 248 240 "inst3" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_decode0.v 1 1 " "Info: Using design file lpm_decode0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode0 " "Info: Found entity 1: lpm_decode0" {  } { { "lpm_decode0.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_decode0.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_decode0 lpm_decode0:inst8 " "Info: Elaborating entity \"lpm_decode0\" for hierarchy \"lpm_decode0:inst8\"" {  } { { "digtalclk.bdf" "inst8" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 192 600 728 304 "inst8" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 62 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_decode lpm_decode0:inst8\|lpm_decode:lpm_decode_component " "Info: Elaborating entity \"lpm_decode\" for hierarchy \"lpm_decode0:inst8\|lpm_decode:lpm_decode_component\"" {  } { { "lpm_decode0.v" "lpm_decode_component" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_decode0.v" 69 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_m0b.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_m0b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_m0b " "Info: Found entity 1: decode_m0b" {  } { { "db/decode_m0b.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/decode_m0b.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decode_m0b lpm_decode0:inst8\|lpm_decode:lpm_decode_component\|decode_m0b:auto_generated " "Info: Elaborating entity \"decode_m0b\" for hierarchy \"lpm_decode0:inst8\|lpm_decode:lpm_decode_component\|decode_m0b:auto_generated\"" {  } { { "lpm_decode.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf" 74 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bin2seg bin2seg:inst9 " "Info: Elaborating entity \"bin2seg\" for hierarchy \"bin2seg:inst9\"" {  } { { "digtalclk.bdf" "inst9" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 360 616 800 456 "inst9" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "lpm_mux0.v 1 1 " "Info: Using design file lpm_mux0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux0 " "Info: Found entity 1: lpm_mux0" {  } { { "lpm_mux0.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_mux0.v" 36 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux0 lpm_mux0:inst7 " "Info: Elaborating entity \"lpm_mux0\" for hierarchy \"lpm_mux0:inst7\"" {  } { { "digtalclk.bdf" "inst7" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 344 464 600 456 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" 72 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_mux lpm_mux0:inst7\|lpm_mux:lpm_mux_component " "Info: Elaborating entity \"lpm_mux\" for hierarchy \"lpm_mux0:inst7\|lpm_mux:lpm_mux_component\"" {  } { { "lpm_mux0.v" "lpm_mux_component" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/lpm_mux0.v" 69 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_9fc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_9fc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_9fc " "Info: Found entity 1: mux_9fc" {  } { { "db/mux_9fc.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/mux_9fc.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux_9fc lpm_mux0:inst7\|lpm_mux:lpm_mux_component\|mux_9fc:auto_generated " "Info: Elaborating entity \"mux_9fc\" for hierarchy \"lpm_mux0:inst7\|lpm_mux:lpm_mux_component\|mux_9fc:auto_generated\"" {  } { { "lpm_mux.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_mux.tdf" 84 3 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ldf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ldf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ldf " "Info: Found entity 1: lpm_divide_ldf" {  } { { "db/lpm_divide_ldf.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/lpm_divide_ldf.tdf" 24 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_khg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_khg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_khg " "Info: Found entity 1: sign_div_unsign_khg" {  } { { "db/sign_div_unsign_khg.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/sign_div_unsign_khg.tdf" 26 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_dld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_dld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_dld " "Info: Found entity 1: alt_u_div_dld" {  } { { "db/alt_u_div_dld.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/alt_u_div_dld.tdf" 32 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ke8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ke8 " "Info: Found entity 1: add_sub_ke8" {  } { { "db/add_sub_ke8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_ke8.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_le8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_le8 " "Info: Found entity 1: add_sub_le8" {  } { { "db/add_sub_le8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/add_sub_le8.tdf" 22 1 0 } }  } 0}  } {  } 0}