digtalclk.map.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(211) " "Warning: Verilog HDL assignment warning at clock.v(211): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 211 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(213) " "Warning: Verilog HDL Always Construct warning at clock.v(213): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 213 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(214) " "Warning: Verilog HDL Always Construct warning at clock.v(214): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 214 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(214) " "Warning: Verilog HDL assignment warning at clock.v(214): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 214 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(216) " "Warning: Verilog HDL Always Construct warning at clock.v(216): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 216 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(216) " "Warning: Verilog HDL assignment warning at clock.v(216): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 216 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(224) " "Warning: Verilog HDL assignment warning at clock.v(224): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 224 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(226) " "Warning: Verilog HDL assignment warning at clock.v(226): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 226 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "pos clock.v(235) " "Warning: Verilog HDL Always Construct warning at clock.v(235): variable \"pos\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 235 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "pos clock.v(237) " "Warning: Verilog HDL Always Construct warning at clock.v(237): variable \"pos\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 237 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "num clock.v(238) " "Warning: Verilog HDL Always Construct warning at clock.v(238): variable \"num\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 238 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(239) " "Warning: Verilog HDL Always Construct warning at clock.v(239): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 239 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(240) " "Warning: Verilog HDL Always Construct warning at clock.v(240): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(240) " "Warning: Verilog HDL assignment warning at clock.v(240): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(242) " "Warning: Verilog HDL assignment warning at clock.v(242): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 242 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(244) " "Warning: Verilog HDL Always Construct warning at clock.v(244): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 244 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(245) " "Warning: Verilog HDL Always Construct warning at clock.v(245): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 245 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(245) " "Warning: Verilog HDL assignment warning at clock.v(245): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 245 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(247) " "Warning: Verilog HDL assignment warning at clock.v(247): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 247 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "num clock.v(249) " "Warning: Verilog HDL Always Construct warning at clock.v(249): variable \"num\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 249 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(250) " "Warning: Verilog HDL Always Construct warning at clock.v(250): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 250 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(251) " "Warning: Verilog HDL Always Construct warning at clock.v(251): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 251 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(251) " "Warning: Verilog HDL assignment warning at clock.v(251): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 251 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(253) " "Warning: Verilog HDL Always Construct warning at clock.v(253): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 253 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(253) " "Warning: Verilog HDL assignment warning at clock.v(253): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 253 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(255) " "Warning: Verilog HDL Always Construct warning at clock.v(255): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 255 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(256) " "Warning: Verilog HDL Always Construct warning at clock.v(256): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 256 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(256) " "Warning: Verilog HDL assignment warning at clock.v(256): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 256 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "h clock.v(258) " "Warning: Verilog HDL Always Construct warning at clock.v(258): variable \"h\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 258 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(258) " "Warning: Verilog HDL assignment warning at clock.v(258): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 258 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(264) " "Warning: Verilog HDL assignment warning at clock.v(264): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 264 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 clock.v(266) " "Warning: Verilog HDL assignment warning at clock.v(266): truncated value with size 32 to match size of target (5)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 266 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(268) " "Warning: Verilog HDL assignment warning at clock.v(268): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 268 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(270) " "Warning: Verilog HDL assignment warning at clock.v(270): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 270 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(282) " "Warning: Verilog HDL assignment warning at clock.v(282): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 282 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(284) " "Warning: Verilog HDL assignment warning at clock.v(284): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 284 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(287) " "Warning: Verilog HDL assignment warning at clock.v(287): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 287 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(289) " "Warning: Verilog HDL assignment warning at clock.v(289): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 289 0 0 } }  } 0}