digtalclk.map.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(94) " "Warning: Verilog HDL assignment warning at clock.v(94): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(95) " "Warning: Verilog HDL assignment warning at clock.v(95): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(107) " "Warning: Verilog HDL assignment warning at clock.v(107): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(108) " "Warning: Verilog HDL assignment warning at clock.v(108): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 108 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(109) " "Warning: Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(110) " "Warning: Verilog HDL assignment warning at clock.v(110): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(114) " "Warning: Verilog HDL assignment warning at clock.v(114): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 114 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 4 clock.v(115) " "Warning: Verilog HDL assignment warning at clock.v(115): truncated value with size 6 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 115 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(116) " "Warning: Verilog HDL assignment warning at clock.v(116): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 116 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 clock.v(117) " "Warning: Verilog HDL assignment warning at clock.v(117): truncated value with size 5 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 117 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(123) " "Warning: Verilog HDL assignment warning at clock.v(123): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(127) " "Warning: Verilog HDL assignment warning at clock.v(127): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 127 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(128) " "Warning: Verilog HDL assignment warning at clock.v(128): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(136) " "Warning: Verilog HDL assignment warning at clock.v(136): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 136 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(137) " "Warning: Verilog HDL assignment warning at clock.v(137): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 137 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(138) " "Warning: Verilog HDL assignment warning at clock.v(138): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 138 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 4 clock.v(139) " "Warning: Verilog HDL assignment warning at clock.v(139): truncated value with size 14 to match size of target (4)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 139 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(147) " "Warning: Verilog HDL assignment warning at clock.v(147): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 147 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 clock.v(150) " "Warning: Verilog HDL assignment warning at clock.v(150): truncated value with size 32 to match size of target (14)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 150 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 clock.v(155) " "Warning: Verilog HDL assignment warning at clock.v(155): truncated value with size 32 to match size of target (14)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 155 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clock.v(171) " "Warning: Verilog HDL assignment warning at clock.v(171): truncated value with size 32 to match size of target (7)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 171 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(173) " "Warning: Verilog HDL assignment warning at clock.v(173): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 173 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(183) " "Warning: Verilog HDL assignment warning at clock.v(183): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 183 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clock.v(185) " "Warning: Verilog HDL assignment warning at clock.v(185): truncated value with size 32 to match size of target (1)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 185 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "pos clock.v(193) " "Warning: Verilog HDL Always Construct warning at clock.v(193): variable \"pos\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 193 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "pos clock.v(195) " "Warning: Verilog HDL Always Construct warning at clock.v(195): variable \"pos\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 195 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "num clock.v(196) " "Warning: Verilog HDL Always Construct warning at clock.v(196): variable \"num\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 196 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(197) " "Warning: Verilog HDL Always Construct warning at clock.v(197): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 197 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(198) " "Warning: Verilog HDL Always Construct warning at clock.v(198): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 198 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(200) " "Warning: Verilog HDL assignment warning at clock.v(200): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 200 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(202) " "Warning: Verilog HDL Always Construct warning at clock.v(202): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 202 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(203) " "Warning: Verilog HDL Always Construct warning at clock.v(203): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 203 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(205) " "Warning: Verilog HDL assignment warning at clock.v(205): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 205 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "num clock.v(207) " "Warning: Verilog HDL Always Construct warning at clock.v(207): variable \"num\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 207 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(208) " "Warning: Verilog HDL Always Construct warning at clock.v(208): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 208 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(209) " "Warning: Verilog HDL Always Construct warning at clock.v(209): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 209 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 clock.v(209) " "Warning: Verilog HDL assignment warning at clock.v(209): truncated value with size 32 to match size of target (6)" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 209 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "m clock.v(211) " "Warning: Verilog HDL Always Construct warning at clock.v(211): variable \"m\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 211 0 0 } }  } 0}