digtalclk.hier_info

用Altera公司的QuartusII编写的电子钟程序

|digtalclk
beep <= inst2.DB_MAX_OUTPUT_PORT_TYPE
clk50mhz => lpm_counter0:inst.clock
ink1 => skey:inst3.keyin
ink2 => skey:inst4.keyin
ink3 => skey:inst5.keyin
ink4 => skey:inst6.keyin
ledcom[0] <= lpm_decode0:inst8.eq0
ledcom[1] <= lpm_decode0:inst8.eq1
ledcom[2] <= lpm_decode0:inst8.eq2
ledcom[3] <= lpm_decode0:inst8.eq3
seg7[0] <= bin2seg:inst9.data_out[0]
seg7[1] <= bin2seg:inst9.data_out[1]
seg7[2] <= bin2seg:inst9.data_out[2]
seg7[3] <= bin2seg:inst9.data_out[3]
seg7[4] <= bin2seg:inst9.data_out[4]
seg7[5] <= bin2seg:inst9.data_out[5]
seg7[6] <= bin2seg:inst9.data_out[6]


|digtalclk|clock:inst1
clk10ms => state[0].CLK
clk10ms => set.CLK
clk10ms => disp[15]~reg0.CLK
clk10ms => disp[14]~reg0.CLK
clk10ms => disp[13]~reg0.CLK
clk10ms => disp[12]~reg0.CLK
clk10ms => disp[11]~reg0.CLK
clk10ms => disp[10]~reg0.CLK
clk10ms => disp[9]~reg0.CLK
clk10ms => disp[8]~reg0.CLK
clk10ms => disp[7]~reg0.CLK
clk10ms => disp[6]~reg0.CLK
clk10ms => disp[5]~reg0.CLK
clk10ms => disp[4]~reg0.CLK
clk10ms => disp[3]~reg0.CLK
clk10ms => disp[2]~reg0.CLK
clk10ms => disp[1]~reg0.CLK
clk10ms => disp[0]~reg0.CLK
clk10ms => pos[1].CLK
clk10ms => pos[0].CLK
clk10ms => num.CLK
clk10ms => alm_set.CLK
clk10ms => run.CLK
clk10ms => sw[13].CLK
clk10ms => sw[12].CLK
clk10ms => sw[11].CLK
clk10ms => sw[10].CLK
clk10ms => sw[9].CLK
clk10ms => sw[8].CLK
clk10ms => sw[7].CLK
clk10ms => sw[6].CLK
clk10ms => sw[5].CLK
clk10ms => sw[4].CLK
clk10ms => sw[3].CLK
clk10ms => sw[2].CLK
clk10ms => sw[1].CLK
clk10ms => sw[0].CLK
clk10ms => lastkey1.CLK
clk10ms => lastkey2.CLK
clk10ms => lastkey3.CLK
clk10ms => lastkey4.CLK
clk10ms => tenms[6].CLK
clk10ms => tenms[5].CLK
clk10ms => tenms[4].CLK
clk10ms => tenms[3].CLK
clk10ms => tenms[2].CLK
clk10ms => tenms[1].CLK
clk10ms => tenms[0].CLK
clk10ms => clk1s.CLK
clk10ms => alm_m[5].CLK
clk10ms => alm_m[4].CLK
clk10ms => alm_m[3].CLK
clk10ms => alm_m[2].CLK
clk10ms => alm_m[1].CLK
clk10ms => alm_m[0].CLK
clk10ms => alm_h[4].CLK
clk10ms => alm_h[3].CLK
clk10ms => alm_h[2].CLK
clk10ms => alm_h[1].CLK
clk10ms => alm_h[0].CLK
clk10ms => lastas.CLK
clk10ms => state[1].CLK
key1 => reduce_nor~1.IN0
key1 => Decoder~0.IN0
key1 => lastkey1.DATAIN
key2 => Decoder~0.IN1
key2 => reduce_nor~4.IN0
key2 => lastkey2.DATAIN
key3 => Decoder~0.IN2
key3 => reduce_nor~2.IN0
key3 => lastkey3.DATAIN
key3 => reduce_nor~5.IN0
key4 => Decoder~0.IN3
key4 => reduce_nor~3.IN0
key4 => lastkey4.DATAIN
disp[0] <= disp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[1] <= disp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[2] <= disp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[3] <= disp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[4] <= disp[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[5] <= disp[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[6] <= disp[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[7] <= disp[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[8] <= disp[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[9] <= disp[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[10] <= disp[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[11] <= disp[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[12] <= disp[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[13] <= disp[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[14] <= disp[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
disp[15] <= disp[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
spk <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|lpm_counter0:inst
clock => clock~0.IN1
q[0] <= lpm_counter:lpm_counter_component.q
q[1] <= lpm_counter:lpm_counter_component.q
q[2] <= lpm_counter:lpm_counter_component.q
q[3] <= lpm_counter:lpm_counter_component.q
q[4] <= lpm_counter:lpm_counter_component.q
q[5] <= lpm_counter:lpm_counter_component.q
q[6] <= lpm_counter:lpm_counter_component.q
q[7] <= lpm_counter:lpm_counter_component.q
q[8] <= lpm_counter:lpm_counter_component.q
q[9] <= lpm_counter:lpm_counter_component.q
q[10] <= lpm_counter:lpm_counter_component.q
q[11] <= lpm_counter:lpm_counter_component.q
q[12] <= lpm_counter:lpm_counter_component.q
q[13] <= lpm_counter:lpm_counter_component.q
q[14] <= lpm_counter:lpm_counter_component.q
q[15] <= lpm_counter:lpm_counter_component.q
q[16] <= lpm_counter:lpm_counter_component.q
q[17] <= lpm_counter:lpm_counter_component.q
q[18] <= lpm_counter:lpm_counter_component.q
cout <= lpm_counter:lpm_counter_component.cout


|digtalclk|lpm_counter0:inst|lpm_counter:lpm_counter_component
clock => cntr_gu8:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
data[8] => ~NO_FANOUT~
data[9] => ~NO_FANOUT~
data[10] => ~NO_FANOUT~
data[11] => ~NO_FANOUT~
data[12] => ~NO_FANOUT~
data[13] => ~NO_FANOUT~
data[14] => ~NO_FANOUT~
data[15] => ~NO_FANOUT~
data[16] => ~NO_FANOUT~
data[17] => ~NO_FANOUT~
data[18] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_gu8:auto_generated.q[0]
q[1] <= cntr_gu8:auto_generated.q[1]
q[2] <= cntr_gu8:auto_generated.q[2]
q[3] <= cntr_gu8:auto_generated.q[3]
q[4] <= cntr_gu8:auto_generated.q[4]
q[5] <= cntr_gu8:auto_generated.q[5]
q[6] <= cntr_gu8:auto_generated.q[6]
q[7] <= cntr_gu8:auto_generated.q[7]
q[8] <= cntr_gu8:auto_generated.q[8]
q[9] <= cntr_gu8:auto_generated.q[9]
q[10] <= cntr_gu8:auto_generated.q[10]
q[11] <= cntr_gu8:auto_generated.q[11]
q[12] <= cntr_gu8:auto_generated.q[12]
q[13] <= cntr_gu8:auto_generated.q[13]
q[14] <= cntr_gu8:auto_generated.q[14]
q[15] <= cntr_gu8:auto_generated.q[15]
q[16] <= cntr_gu8:auto_generated.q[16]
q[17] <= cntr_gu8:auto_generated.q[17]
q[18] <= cntr_gu8:auto_generated.q[18]
cout <= cntr_gu8:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|digtalclk|lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
clock => counter_cella8.CLK
clock => counter_cella9.CLK
clock => counter_cella10.CLK
clock => counter_cella11.CLK
clock => counter_cella12.CLK
clock => counter_cella13.CLK
clock => counter_cella14.CLK
clock => counter_cella15.CLK
clock => counter_cella16.CLK
clock => counter_cella17.CLK
clock => counter_cella18.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT
q[8] <= counter_cella8.REGOUT
q[9] <= counter_cella9.REGOUT
q[10] <= counter_cella10.REGOUT
q[11] <= counter_cella11.REGOUT
q[12] <= counter_cella12.REGOUT
q[13] <= counter_cella13.REGOUT
q[14] <= counter_cella14.REGOUT
q[15] <= counter_cella15.REGOUT
q[16] <= counter_cella16.REGOUT
q[17] <= counter_cella17.REGOUT
q[18] <= counter_cella18.REGOUT


|digtalclk|skey:inst3
keyin => keyreg[0].DATAIN
clk => keyreg[4].CLK
clk => keyreg[3].CLK
clk => keyreg[2].CLK
clk => keyreg[1].CLK
clk => keyreg[0].CLK
clk => keyout~reg0.CLK
keyout <= keyout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|skey:inst4
keyin => keyreg[0].DATAIN
clk => keyreg[4].CLK
clk => keyreg[3].CLK
clk => keyreg[2].CLK
clk => keyreg[1].CLK
clk => keyreg[0].CLK
clk => keyout~reg0.CLK
keyout <= keyout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|skey:inst5
keyin => keyreg[0].DATAIN
clk => keyreg[4].CLK
clk => keyreg[3].CLK
clk => keyreg[2].CLK
clk => keyreg[1].CLK
clk => keyreg[0].CLK
clk => keyout~reg0.CLK
keyout <= keyout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|skey:inst6
keyin => keyreg[0].DATAIN
clk => keyreg[4].CLK
clk => keyreg[3].CLK
clk => keyreg[2].CLK
clk => keyreg[1].CLK
clk => keyreg[0].CLK
clk => keyout~reg0.CLK
keyout <= keyout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|lpm_decode0:inst8
data[0] => data[0]~1.IN1
data[1] => data[1]~0.IN1
eq0 <= lpm_decode:lpm_decode_component.eq
eq1 <= lpm_decode:lpm_decode_component.eq
eq2 <= lpm_decode:lpm_decode_component.eq
eq3 <= lpm_decode:lpm_decode_component.eq


|digtalclk|lpm_decode0:inst8|lpm_decode:lpm_decode_component
data[0] => decode_m0b:auto_generated.data[0]
data[1] => decode_m0b:auto_generated.data[1]
enable => ~NO_FANOUT~
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
eq[0] <= decode_m0b:auto_generated.eq[0]
eq[1] <= decode_m0b:auto_generated.eq[1]
eq[2] <= decode_m0b:auto_generated.eq[2]
eq[3] <= decode_m0b:auto_generated.eq[3]


|digtalclk|lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated
data[0] => w_anode15w[1].IN1
data[0] => w_anode33w[1].IN1
data[1] => w_anode24w[2].IN1
data[1] => w_anode33w[2].IN1
eq[0] <= w_anode1w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode15w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode24w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode33w[2].DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|bin2seg:inst9
data_in[0] => Decoder~0.IN3
data_in[1] => Decoder~0.IN2
data_in[2] => Decoder~0.IN1
data_in[3] => Decoder~0.IN0
data_out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
data_out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
data_out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
data_out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
data_out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
data_out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
data_out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE


|digtalclk|lpm_mux0:inst7
data3x[0] => sub_wire2[12].IN1
data3x[1] => sub_wire2[13].IN1
data3x[2] => sub_wire2[14].IN1
data3x[3] => sub_wire2[15].IN1
data2x[0] => sub_wire2[8].IN1
data2x[1] => sub_wire2[9].IN1
data2x[2] => sub_wire2[10].IN1
data2x[3] => sub_wire2[11].IN1
data1x[0] => sub_wire2[4].IN1
data1x[1] => sub_wire2[5].IN1
data1x[2] => sub_wire2[6].IN1
data1x[3] => sub_wire2[7].IN1
data0x[0] => sub_wire2[0].IN1
data0x[1] => sub_wire2[1].IN1
data0x[2] => sub_wire2[2].IN1
data0x[3] => sub_wire2[3].IN1
sel[0] => sel[0]~1.IN1
sel[1] => sel[1]~0.IN1
result[0] <= lpm_mux:lpm_mux_component.result
result[1] <= lpm_mux:lpm_mux_component.result
result[2] <= lpm_mux:lpm_mux_component.result
result[3] <= lpm_mux:lpm_mux_component.result


|digtalclk|lpm_mux0:inst7|lpm_mux:lpm_mux_component
data[0][0] => mux_9fc:auto_generated.data[0]
data[0][1] => mux_9fc:auto_generated.data[1]
data[0][2] => mux_9fc:auto_generated.data[2]
data[0][3] => mux_9fc:auto_generated.data[3]
data[1][0] => mux_9fc:auto_generated.data[4]
data[1][1] => mux_9fc:auto_generated.data[5]
data[1][2] => mux_9fc:auto_generated.data[6]
data[1][3] => mux_9fc:auto_generated.data[7]
data[2][0] => mux_9fc:auto_generated.data[8]
data[2][1] => mux_9fc:auto_generated.data[9]
data[2][2] => mux_9fc:auto_generated.data[10]
data[2][3] => mux_9fc:auto_generated.data[11]
data[3][0] => mux_9fc:auto_generated.data[12]
data[3][1] => mux_9fc:auto_generated.data[13]
data[3][2] => mux_9fc:auto_generated.data[14]
data[3][3] => mux_9fc:auto_generated.data[15]
sel[0] => mux_9fc:auto_generated.sel[0]
sel[1] => mux_9fc:auto_generated.sel[1]
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= mux_9fc:auto_generated.result[0]
result[1] <= mux_9fc:auto_generated.result[1]
result[2] <= mux_9fc:auto_generated.result[2]
result[3] <= mux_9fc:auto_generated.result[3]


|digtalclk|lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated
result[0] <= w_result15w.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= w_result45w.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= w_result70w.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= w_result95w.DB_MAX_OUTPUT_PORT_TYPE