mux_9fc.tdf

用Altera公司的QuartusII编写的电子钟程序

--lpm_mux CASCADE_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=4 LPM_WIDTH=4 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_9fc
( 
	data[15..0]	:	input;
	result[3..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[3..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data34w[3..0]	: WIRE;
	w_data4w[3..0]	: WIRE;
	w_data59w[3..0]	: WIRE;
	w_data84w[3..0]	: WIRE;
	w_result15w	: WIRE;
	w_result16w	: WIRE;
	w_result35w	: WIRE;
	w_result45w	: WIRE;
	w_result46w	: WIRE;
	w_result5w	: WIRE;
	w_result60w	: WIRE;
	w_result70w	: WIRE;
	w_result71w	: WIRE;
	w_result85w	: WIRE;
	w_result95w	: WIRE;
	w_result96w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result85w, w_result60w, w_result35w, w_result5w);
	sel_node[] = ( sel[1..0]);
	w_data34w[] = ( data[13..13], data[9..9], data[5..5], data[1..1]);
	w_data4w[] = ( data[12..12], data[8..8], data[4..4], data[0..0]);
	w_data59w[] = ( data[14..14], data[10..10], data[6..6], data[2..2]);
	w_data84w[] = ( data[15..15], data[11..11], data[7..7], data[3..3]);
	w_result15w = (((w_data4w[1..1] & sel_node[0..0]) & (! w_result16w)) # (w_result16w & (w_data4w[3..3] # (! sel_node[0..0]))));
	w_result16w = (((w_data4w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data4w[2..2])));
	w_result35w = w_result45w;
	w_result45w = (((w_data34w[1..1] & sel_node[0..0]) & (! w_result46w)) # (w_result46w & (w_data34w[3..3] # (! sel_node[0..0]))));
	w_result46w = (((w_data34w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data34w[2..2])));
	w_result5w = w_result15w;
	w_result60w = w_result70w;
	w_result70w = (((w_data59w[1..1] & sel_node[0..0]) & (! w_result71w)) # (w_result71w & (w_data59w[3..3] # (! sel_node[0..0]))));
	w_result71w = (((w_data59w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data59w[2..2])));
	w_result85w = w_result95w;
	w_result95w = (((w_data84w[1..1] & sel_node[0..0]) & (! w_result96w)) # (w_result96w & (w_data84w[3..3] # (! sel_node[0..0]))));
	w_result96w = (((w_data84w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data84w[2..2])));
END;
--VALID FILE