digtalclk.fit.qmsg

用Altera公司的QuartusII编写的电子钟程序

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|safe_q\[15\] Global clock " "Info: Automatically promoted some destinations of signal \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|safe_q\[15\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|counter_cella15 " "Info: Destination \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|counter_cella15\" may be non-global or may not use global clock" {  } { { "db/cntr_gu8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/cntr_gu8.tdf" 205 8 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "inst2~83 " "Info: Destination \"inst2~83\" may be non-global or may not use global clock" {  } { { "digtalclk.bdf" "" { Schematic "D:/Study/大4/近代电子学试验QuartusII/digtalclk/digtalclk.bdf" { { 112 608 672 160 "inst2" "" } } } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|cmpr1_aeb_int~139 " "Info: Destination \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_gu8:auto_generated\|cmpr1_aeb_int~139\" may be non-global or may not use global clock" {  } { { "db/cntr_gu8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/cntr_gu8.tdf" 32 2 0 } }  } 0}  } { { "db/cntr_gu8.tdf" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/db/cntr_gu8.tdf" 205 8 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock:inst1\|clk1m Global clock " "Info: Automatically promoted some destinations of signal \"clock:inst1\|clk1m\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|clk1m " "Info: Destination \"clock:inst1\|clk1m\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|clk1m~204 " "Info: Destination \"clock:inst1\|clk1m~204\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock:inst1\|clk1s Global clock " "Info: Automatically promoted some destinations of signal \"clock:inst1\|clk1s\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[8\] " "Info: Destination \"clock:inst1\|disp\[8\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[4\] " "Info: Destination \"clock:inst1\|disp\[4\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[12\] " "Info: Destination \"clock:inst1\|disp\[12\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[0\] " "Info: Destination \"clock:inst1\|disp\[0\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[5\] " "Info: Destination \"clock:inst1\|disp\[5\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[9\] " "Info: Destination \"clock:inst1\|disp\[9\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[13\] " "Info: Destination \"clock:inst1\|disp\[13\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[1\] " "Info: Destination \"clock:inst1\|disp\[1\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[10\] " "Info: Destination \"clock:inst1\|disp\[10\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|disp\[6\] " "Info: Destination \"clock:inst1\|disp\[6\]\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock:inst1\|clk1h Global clock " "Info: Automatically promoted some destinations of signal \"clock:inst1\|clk1h\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|clk1h " "Info: Destination \"clock:inst1\|clk1h\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|clk1h~216 " "Info: Destination \"clock:inst1\|clk1h~216\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clock:inst1\|set Global clock " "Info: Automatically promoted some destinations of signal \"clock:inst1\|set\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|clk1h " "Info: Destination \"clock:inst1\|clk1h\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clock:inst1\|set " "Info: Destination \"clock:inst1\|set\" may be non-global or may not use global clock" {  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}  } { { "clock.v" "" { Text "D:/Study/大4/近代电子学试验QuartusII/digtalclk/clock.v" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}