skey.v

来自「用Altera公司的QuartusII编写的电子钟程序」· Verilog 代码 · 共 14 行

module skey(keyin,clk,keyout);
input keyin,clk;
output keyout;
reg keyout;
reg [4:0]keyreg;
always @(posedge clk)
begin
	keyout=&keyreg;
	keyreg={keyreg[3:0],keyin};
end
//assign keyout=(&keyreg)? 1'b1:keyout;
//assign keyout=(~|keyreg)? 1'b0:keyout; 
endmodule