digtalclk.tan.summary

用Altera公司的QuartusII编写的电子钟程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.726 ns
From           : ink3
To             : skey:inst5|keyreg[0]
From Clock     : 
To Clock       : clk50mhz
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 35.925 ns
From           : clock:inst1|h[4]
To             : beep
From Clock     : clk50mhz
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.832 ns
From           : ink4
To             : skey:inst6|keyreg[0]
From Clock     : 
To Clock       : clk50mhz
Failed Paths   : 0

Type           : Clock Setup: 'clk50mhz'
Slack          : N/A
Required Time  : None
Actual Time    : 18.51 MHz ( period = 54.013 ns )
From           : clock:inst1|sw[11]
To             : clock:inst1|disp[7]
From Clock     : clk50mhz
To Clock       : clk50mhz
Failed Paths   : 0

Type           : Clock Hold: 'clk50mhz'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : clock:inst1|set
To             : clock:inst1|clk1h
From Clock     : clk50mhz
To Clock       : clk50mhz
Failed Paths   : 130

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 130

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