digtalclk.map.rpt

用Altera公司的QuartusII编写的电子钟程序

Analysis & Synthesis report for digtalclk
Mon Oct 29 21:15:36 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Multiplexer Restructuring Statistics (Restructuring Performed)
  9. Parameter Settings for User Entity Instance: lpm_counter0:inst|lpm_counter:lpm_counter_component
 10. Parameter Settings for User Entity Instance: lpm_decode0:inst8|lpm_decode:lpm_decode_component
 11. Parameter Settings for User Entity Instance: lpm_mux0:inst7|lpm_mux:lpm_mux_component
 12. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_0
 13. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_1
 14. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_2
 15. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_3
 16. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_4
 17. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_5
 18. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_6
 19. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_7
 20. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_8
 21. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_9
 22. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_10
 23. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_11
 24. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_12
 25. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_13
 26. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_14
 27. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_15
 28. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:div_rtl_16
 29. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_17
 30. Parameter Settings for Inferred Entity Instance: clock:inst1|lpm_divide:mod_rtl_18
 31. Analysis & Synthesis Equations
 32. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Oct 29 21:15:36 2007    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; digtalclk                                ;
; Top-level Entity Name       ; digtalclk                                ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 1,541                                    ;