digtalclk.map.eqn

用Altera公司的QuartusII编写的电子钟程序

C1L033 = C1L221 # C1L823 & (!D3_keyout # !D4_keyout);


--C1L133 is clock:inst1|disp[12]~1033
--operation mode is normal

C1L133 = C1L321 & (C1L033 & C1L723 # !C1L033 & (C1L923)) # !C1L321 & (C1L923);


--C1_s[0] is clock:inst1|s[0]
--operation mode is normal

C1_s[0]_lut_out = C1L551 & C1L22;
C1_s[0] = DFFEAS(C1_s[0]_lut_out, C1_clk1s, VCC, , , , , , );


--X7L1 is clock:inst1|lpm_divide:div_rtl_5|lpm_divide_4nf:auto_generated|sign_div_unsign_6jg:divider|alt_u_div_hod:divider|add_sub_re8:add_sub_13|add_sub_cella[3]~61
--operation mode is normal

X7L1_carry_eqn = X7L3;
X7L1 = !X7L1_carry_eqn;


--C1L62 is clock:inst1|Select~1426
--operation mode is normal

C1L62 = C1L133 & (C1L333) # !C1L133 & (C1L333 & C1_s[0] # !C1L333 & (X7L1));


--C1L72 is clock:inst1|Select~1427
--operation mode is normal

C1L72 = C1L133 & (C1L62 & (C1_alm_h[0]) # !C1L62 & C1_h[0]) # !C1L133 & (C1L62);


--C1L123 is clock:inst1|disp[8]~1034
--operation mode is normal

C1L123 = C1_state[1] $ (C1_state[0] # C1_lastkey1 & !D1_keyout);


--C1_clk1s is clock:inst1|clk1s
--operation mode is normal

C1_clk1s_lut_out = C1L302 & (!C1L803 # !C1L42) # !C1L302 & (C1_clk1s);
C1_clk1s = DFFEAS(C1_clk1s_lut_out, J1_modulus_trigger, VCC, , , , , , );


--C1_lastkey2 is clock:inst1|lastkey2
--operation mode is normal

C1_lastkey2_lut_out = D2_keyout;
C1_lastkey2 = DFFEAS(C1_lastkey2_lut_out, J1_modulus_trigger, VCC, , , , , , );


--C1L421 is clock:inst1|add~4286
--operation mode is normal

C1L421 = C1_pos[0] $ (D2_keyout # !C1_lastkey2);


--C1L521 is clock:inst1|add~4287
--operation mode is normal

C1L521 = C1_pos[1] $ (!D2_keyout & C1_pos[0] & C1_lastkey2);


--C1L223 is clock:inst1|disp[8]~1035
--operation mode is normal

C1L223 = C1L421 & C1L521 # !C1_clk1s # !C1L123;


--U4L1 is clock:inst1|lpm_divide:div_rtl_7|lpm_divide_jlf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

U4L1_carry_eqn = U4L3;
U4L1 = !U4L1_carry_eqn;


--U6L1 is clock:inst1|lpm_divide:div_rtl_8|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

U6L1_carry_eqn = U6L3;
U6L1 = !U6L1_carry_eqn;


--U61L1 is clock:inst1|lpm_divide:div_rtl_9|lpm_divide_1nf:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[2]~41
--operation mode is normal

U61L1_carry_eqn = U61L3;
U61L1 = !U61L1_carry_eqn;


--C1L82 is clock:inst1|Select~1429
--operation mode is normal

C1L82 = C1L333 & (C1L133) # !C1L333 & (C1L133 & U6L1 # !C1L133 & (U61L1));


--U81L1 is clock:inst1|lpm_divide:div_rtl_11|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

U81L1_carry_eqn = U81L3;
U81L1 = !U81L1_carry_eqn;


--C1L92 is clock:inst1|Select~1430
--operation mode is normal

C1L92 = C1L333 & (C1L82 & (U81L1) # !C1L82 & U4L1) # !C1L333 & (C1L82);


--C1L813 is clock:inst1|disp[6]~1036
--operation mode is normal

C1L813 = !C1L421 & !C1L521 # !C1_clk1s # !C1L123;


--U91L1 is clock:inst1|lpm_divide:div_rtl_12|lpm_divide_hlf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U91L1_carry_eqn = U91L3;
U91L1 = !U91L1_carry_eqn;


--U12L1 is clock:inst1|lpm_divide:div_rtl_13|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

U12L1_carry_eqn = U12L3;
U12L1 = !U12L1_carry_eqn;


--TB4L1 is clock:inst1|lpm_divide:div_rtl_14|lpm_divide_eof:auto_generated|sign_div_unsign_gkg:divider|alt_u_div_5rd:divider|add_sub_5g8:add_sub_13|add_sub_cella[4]~81
--operation mode is normal

TB4L1_carry_eqn = TB4L3;
TB4L1 = !TB4L1_carry_eqn;


--C1L03 is clock:inst1|Select~1432
--operation mode is normal

C1L03 = C1L133 & (C1L333) # !C1L133 & (C1L333 & U12L1 # !C1L333 & (TB4L1));


--U32L1 is clock:inst1|lpm_divide:div_rtl_16|lpm_divide_hlf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U32L1_carry_eqn = U32L3;
U32L1 = !U32L1_carry_eqn;


--C1L13 is clock:inst1|Select~1433
--operation mode is normal

C1L13 = C1L133 & (C1L03 & (U32L1) # !C1L03 & U91L1) # !C1L133 & (C1L03);


--C1L233 is clock:inst1|disp[12]~1037
--operation mode is normal

C1L233 = C1L521 & !C1L421 # !C1_clk1s # !C1L123;


--C1_tenms[0] is clock:inst1|tenms[0]
--operation mode is normal

C1_tenms[0]_lut_out = C1L202;
C1_tenms[0] = DFFEAS(C1_tenms[0]_lut_out, J1_modulus_trigger, VCC, , , , , , );


--C1_sw[0] is clock:inst1|sw[0]
--operation mode is arithmetic

C1_sw[0]_lut_out = C1L364 $ C1L514;
C1_sw[0] = DFFEAS(C1_sw[0]_lut_out, J1_modulus_trigger, VCC, , C1L2, , , C1L444, );

--C1L134 is clock:inst1|sw[0]~553
--operation mode is arithmetic

C1L134 = CARRY(C1L364 & C1L514);


--C1L23 is clock:inst1|Select~1435
--operation mode is normal

C1L23 = C1L333 & (C1L133) # !C1L333 & (C1L133 & C1_m[0] # !C1L133 & (C1_sw[0]));


--C1L33 is clock:inst1|Select~1436
--operation mode is normal

C1L33 = C1L333 & (C1L23 & (C1_alm_m[0]) # !C1L23 & C1_tenms[0]) # !C1L333 & (C1L23);


--C1L213 is clock:inst1|disp[1]~1038
--operation mode is normal

C1L213 = C1L421 & !C1L521 # !C1_clk1s # !C1L123;


--U3L4 is clock:inst1|lpm_divide:div_rtl_7|lpm_divide_jlf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

U3L4_carry_eqn = U3L6;
U3L4 = !U3L4_carry_eqn;


--U5L4 is clock:inst1|lpm_divide:div_rtl_8|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U5L4_carry_eqn = U5L6;
U5L4 = !U5L4_carry_eqn;


--U51L4 is clock:inst1|lpm_divide:div_rtl_9|lpm_divide_1nf:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_12|add_sub_cella[2]~42
--operation mode is normal

U51L4_carry_eqn = U51L6;
U51L4 = !U51L4_carry_eqn;


--U15L4 is clock:inst1|lpm_divide:mod_rtl_10|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[2]~41
--operation mode is normal

U15L4_carry_eqn = U15L01;
U15L4 = !U15L4_carry_eqn;


--U15_add_sub_cella[1] is clock:inst1|lpm_divide:mod_rtl_10|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]
--operation mode is arithmetic

U15_add_sub_cella[1] = U51L4;

--U15L3 is clock:inst1|lpm_divide:mod_rtl_10|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]~COUT
--operation mode is arithmetic

U15L3 = CARRY(U51L4);


--HB3L34 is clock:inst1|lpm_divide:mod_rtl_10|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|StageOut[66]~1290
--operation mode is normal

HB3L34 = U15L4 & (!U15_add_sub_cella[1]) # !U15L4 & U51L4;


--C1L43 is clock:inst1|Select~1438
--operation mode is normal

C1L43 = C1L333 & (C1L133) # !C1L333 & (C1L133 & U5L4 # !C1L133 & (HB3L34));


--U71L4 is clock:inst1|lpm_divide:div_rtl_11|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U71L4_carry_eqn = U71L6;
U71L4 = !U71L4_carry_eqn;


--C1L53 is clock:inst1|Select~1439
--operation mode is normal

C1L53 = C1L333 & (C1L43 & (U71L4) # !C1L43 & U3L4) # !C1L333 & (C1L43);


--LB4L7 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[21]~301
--operation mode is normal

LB4L7 = U92L4 $ C1_h[1];


--U13L2 is clock:inst1|lpm_divide:mod_rtl_4|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is normal

U13L2_carry_eqn = U13L8;
U13L2 = !U13L2_carry_eqn;


--C1_s[1] is clock:inst1|s[1]
--operation mode is arithmetic

C1_s[1]_lut_out = C1L541;
C1_s[1] = DFFEAS(C1_s[1]_lut_out, C1_clk1s, VCC, , , , , , );

--U13L1 is clock:inst1|lpm_divide:mod_rtl_4|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

U13L1 = CARRY(C1_s[1]);


--EB6L31 is clock:inst1|lpm_divide:mod_rtl_4|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[26]~460
--operation mode is normal

EB6L31 = U13L2 $ C1_s[1];


--X6L4 is clock:inst1|lpm_divide:div_rtl_5|lpm_divide_4nf:auto_generated|sign_div_unsign_6jg:divider|alt_u_div_hod:divider|add_sub_re8:add_sub_12|add_sub_cella[3]~62
--operation mode is normal

X6L4_carry_eqn = X6L6;
X6L4 = !X6L4_carry_eqn;


--U14L4 is clock:inst1|lpm_divide:mod_rtl_6|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[2]~41
--operation mode is normal

U14L4_carry_eqn = U14L01;
U14L4 = !U14L4_carry_eqn;


--U14_add_sub_cella[1] is clock:inst1|lpm_divide:mod_rtl_6|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]
--operation mode is arithmetic

U14_add_sub_cella[1] = X6L4;

--U14L3 is clock:inst1|lpm_divide:mod_rtl_6|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]~COUT
--operation mode is arithmetic

U14L3 = CARRY(X6L4);


--HB2L52 is clock:inst1|lpm_divide:mod_rtl_6|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|StageOut[66]~840
--operation mode is normal

HB2L52 = U14L4 & (!U14_add_sub_cella[1]) # !U14L4 & X6L4;


--C1L63 is clock:inst1|Select~1441
--operation mode is normal

C1L63 = C1L133 & (C1L333) # !C1L133 & (C1L333 & EB6L31 # !C1L333 & (HB2L52));


--LB3L7 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[21]~312
--operation mode is normal

LB3L7 = U82L4 $ C1_alm_h[1];


--C1L73 is clock:inst1|Select~1442
--operation mode is normal

C1L73 = C1L133 & (C1L63 & (LB3L7) # !C1L63 & LB4L7) # !C1L133 & (C1L63);


--T6L4 is clock:inst1|lpm_divide:div_rtl_12|lpm_divide_hlf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T6L4_carry_eqn = T6L6;
T6L4 = T6L4_carry_eqn;


--U02L4 is clock:inst1|lpm_divide:div_rtl_13|lpm_divide_ilf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U02L4_carry_eqn = U02L6;
U02L4 = !U02L4_carry_eqn;


--TB3L4 is clock:inst1|lpm_divide:div_rtl_14|lpm_divide_eof:auto_generated|sign_div_unsign_gkg:divider|alt_u_div_5rd:divider|add_sub_5g8:add_sub_12|add_sub_cella[4]~82
--operation mode is normal

TB3L4_carry_eqn = TB3L6;
TB3L4 = !TB3L4_carry_eqn;


--U16L4 is clock:inst1|lpm_divide:mod_rtl_15|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[2]~41
--operation mode is normal

U16L4_carry_eqn = U16L01;
U16L4 = !U16L4_carry_eqn;


--U16_add_sub_cella[1] is clock:inst1|lpm_divide:mod_rtl_15|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]
--operation mode is arithmetic

U16_add_sub_cella[1] = TB3L4;

--U16L3 is clock:inst1|lpm_divide:mod_rtl_15|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[1]~COUT
--operation mode is arithmetic

U16L3 = CARRY(TB3L4);


--HB4L7 is clock:inst1|lpm_divide:mod_rtl_15|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|StageOut[66]~344
--operation mode is normal

HB4L7 = U16L4 & (!U16_add_sub_cella[1]) # !U16L4 & TB3L4;


--C1L83 is clock:inst1|Select~1444
--operation mode is normal

C1L83 = C1L133 & (C1L333) # !C1L133 & (C1L333 & U02L4 # !C1L333 & (HB4L7));


--T9L4 is clock:inst1|lpm_divide:div_rtl_16|lpm_divide_hlf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T9L4_carry_eqn = T9L6;
T9L4 = T9L4_carry_eqn;


--C1L93 is clock:inst1|Select~1445
--operation mode is normal

C1L93 = C1L133 & (C1L83 & (T9L4) # !C1L83 & T6L4) # !C1L133 & (C1L83);


--U46L4 is clock:inst1|lpm_divide:mod_rtl_17|lpm_divide_mdf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~41
--operation mode is normal

U46L4_carry_eqn = U46L01;
U46L4 = !U46L4_carry_eqn;


--U46_add_sub_cella[1] is clock:inst1|lpm_divide:mod_rtl_17|lpm_divide_mdf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]
--operation mode is arithmetic

U46_add_sub_cella[1] = C1_tenms[1];

--U46L3 is clock:inst1|lpm_divide:mod_rtl_17|lpm_divide_mdf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|add_sub_oe8:add_sub_6|add_sub_cella[1]~COUT
--operation mode is arithmetic

U46L3 = CARRY(U46_add_sub_cella[1]);


--BB2L91 is clock:inst1|lpm_divide:mod_rtl_17|lpm_divide_mdf:auto_generated|sign_div_unsign_lhg:divider|alt_u_div_fld:divider|StageOut[31]~620
--operation mode is normal

BB2L91 = U46L4 $ U46_add_sub_cella[1];


--C1_sw[1] is clock:inst1|sw[1]
--operation mode is arithmetic

C1_sw[1]_carry_eqn = C1L134;
C1_sw[1]_lut_out = C1_sw[1]_carry_eqn $ (C1_sw[1] & C1L264);
C1_sw[1] = DFFEAS(C1_sw[1]_lut_out, J1_modulus_trigger, VCC, , C1L2, , , C1L444, );

--C1L334 is clock:inst1|sw[1]~557
--operation mode is arithmetic

C1L334 = CARRY(!C1L134 # !C1L264 # !C1_sw[1]);


--U47L4 is clock:inst1|lpm_divide:mod_rtl_18|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bod:divider|add_sub_oe8:add_sub_13|add_sub_cella[2]~41
--operation mode is normal

U47L4_carry_eqn = U47L01;
U47L4 = !U47L4_carry_eqn;


--U47_add_sub_cella[1] is clock:inst1|lpm_divide:mod_rtl_18|lpm_divide_4ff:auto_generated|sign_div_unsign_3jg:divider|alt_u_div_bo