digtalclk.map.eqn

用Altera公司的QuartusII编写的电子钟程序

--operation mode is normal

C1L242 = C1_num & (!C1_pos[0]) # !C1_num & (C1_alm_h[4] # C1L142);


--C1L342 is clock:inst1|alm_h[3]~1816
--operation mode is normal

C1L342 = C1_num & (C1L9 # !C1_pos[0]);


--C1L842 is clock:inst1|alm_h~1817
--operation mode is normal

C1L842 = C1L242 & (C1L342 & (C1L76) # !C1L342 & C1L56) # !C1L242 & (C1L342);


--C1L942 is clock:inst1|alm_h~1818
--operation mode is normal

C1L942 = C1L862 & (C1L842 & (!C1L46) # !C1L842 & LB3L9) # !C1L862 & (C1L842);


--C1L01 is clock:inst1|LessThan~1393
--operation mode is normal

C1L01 = !C1_alm_h[3] & (!C1_alm_h[2] # !C1_alm_h[1] # !C1_alm_h[0]);


--C1L442 is clock:inst1|alm_h[3]~1819
--operation mode is normal

C1L442 = C1L862 # C1L01 # !C1L342 # !C1_alm_h[4];


--C1L642 is clock:inst1|alm_h[4]~1821
--operation mode is normal

C1L642 = C1_pos[1] & C1_lastas & (!C1_alm_set);


--C1L96 is clock:inst1|add~4145
--operation mode is arithmetic

C1L96_carry_eqn = C1L131;
C1L96 = C1_h[3] $ (C1L96_carry_eqn);

--C1L07 is clock:inst1|add~4147
--operation mode is arithmetic

C1L07 = CARRY(!C1L131 # !C1_h[3]);


--C1L17 is clock:inst1|add~4150
--operation mode is normal

C1L17 = C1L96 & C1L81;


--C1_clk1h is clock:inst1|clk1h
--operation mode is normal

C1_clk1h_lut_out = C1L431 & C1_clk1h & (!C1L303 # !C1L731) # !C1L431 & (C1_clk1h # !C1L731 & !C1L303);
C1_clk1h = DFFEAS(C1_clk1h_lut_out, C1_clk1m, VCC, , C1_set, , , , );


--U92L2 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is arithmetic

U92L2_carry_eqn = U92L6;
U92L2 = U92L2_carry_eqn $ (!LB4L3 & !LB4L4);

--U92L3 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~43
--operation mode is arithmetic

U92L3 = CARRY(!U92L6 & (LB4L3 # LB4L4));


--T31L2 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T31L2_carry_eqn = T31L6;
T31L2 = T31L2_carry_eqn;


--T31L3 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~37
--operation mode is arithmetic

T31L3_carry_eqn = T31L8;
T31L3 = C1_h[3] $ (!T31L3_carry_eqn);

--T31L4 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~39
--operation mode is arithmetic

T31L4 = CARRY(!C1_h[3] & (!T31L8));


--LB4L4 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[17]~17
--operation mode is normal

LB4L4 = T31L2 & T31L3;


--LB4L3 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[17]~12
--operation mode is normal

LB4L3 = C1_h[3] & (!T31L2);


--U92L4 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~46
--operation mode is normal

U92L4_carry_eqn = U92L8;
U92L4 = !U92L4_carry_eqn;


--LB4L9 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[23]~299
--operation mode is normal

LB4L9 = U92L4 & U92L2 # !U92L4 & (LB4L4 # LB4L3);


--U92L5 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~51
--operation mode is arithmetic

U92L5_carry_eqn = U92L01;
U92L5 = U92L5_carry_eqn $ (!LB4L1 & !LB4L2);

--U92L6 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~53
--operation mode is arithmetic

U92L6 = CARRY(!LB4L1 & !LB4L2 & !U92L01);


--LB4L8 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[22]~300
--operation mode is normal

LB4L8 = U92L4 & U92L5 # !U92L4 & (T31L2 $ C1_h[2]);


--C1L27 is clock:inst1|add~4151
--operation mode is normal

C1L27 = LB4L8 & (U92L4 $ C1_h[1]);


--C1L343 is clock:inst1|h~1237
--operation mode is normal

C1L343 = C1_pos[0] & C1_pos[1] & (!C1_num);


--C1L37 is clock:inst1|add~4152
--operation mode is normal

C1L37 = C1_h[3] $ (C1_h[1] & C1_h[2]);


--C1L47 is clock:inst1|add~4153
--operation mode is arithmetic

C1L47_carry_eqn = C1L241;
C1L47 = C1_h[3] $ (!C1L47_carry_eqn);

--C1L57 is clock:inst1|add~4155
--operation mode is arithmetic

C1L57 = CARRY(!C1_h[3] & (!C1L241));


--C1L443 is clock:inst1|h~1238
--operation mode is normal

C1L443 = C1_h[3] # C1_h[0] # C1_h[1] # C1_h[4];


--C1L543 is clock:inst1|h~1239
--operation mode is normal

C1L543 = C1_num & (!C1_pos[0]) # !C1_num & (C1_h[2] # C1L443);


--C1L11 is clock:inst1|LessThan~1395
--operation mode is normal

C1L11 = C1_h[3] & (C1_h[1] # C1_h[2]);


--C1L643 is clock:inst1|h~1240
--operation mode is normal

C1L643 = C1_num & (!C1_h[4] & !C1L11 # !C1_pos[0]);


--C1L743 is clock:inst1|h~1241
--operation mode is normal

C1L743 = C1L543 & (C1L643 & (C1L17) # !C1L643 & C1L47) # !C1L543 & (C1L643);


--C1L843 is clock:inst1|h~1242
--operation mode is normal

C1L843 = C1L862 & (C1L743 & (!C1L37) # !C1L743 & LB4L9) # !C1L862 & (C1L743);


--C1L943 is clock:inst1|h~1243
--operation mode is normal

C1L943 = C1_pos[1] & (C1_h[4] # C1L11 # !C1L762);


--C1L053 is clock:inst1|h~1244
--operation mode is normal

C1L053 = C1L343 & (C1L943) # !C1L343 & (C1L943 & C1L843 # !C1L943 & (C1_h[3]));


--C1L67 is clock:inst1|add~4158
--operation mode is normal

C1L67 = C1_h[3] $ (C1_h[1] # C1_h[2]);


--C1L153 is clock:inst1|h~1245
--operation mode is normal

C1L153 = C1L343 & (C1L053 & (C1L67) # !C1L053 & !C1L232) # !C1L343 & (C1L053);


--C1_set is clock:inst1|set
--operation mode is normal

C1_set_lut_out = C1L321 # C1L221 & C1_set # !C1L221 & (C1L424);
C1_set = DFFEAS(C1_set_lut_out, J1_modulus_trigger, VCC, , , , , , );


--C1L77 is clock:inst1|add~4159
--operation mode is normal

C1L77_carry_eqn = C1L19;
C1L77 = C1_m[5] $ (C1L77_carry_eqn);


--C1L87 is clock:inst1|add~4164
--operation mode is normal

C1L87 = C1L77 & C1L02;


--C1_clk1m is clock:inst1|clk1m
--operation mode is normal

C1_clk1m_lut_out = C1L541 & C1_clk1m & (!C1L603 # !C1L841) # !C1L541 & (C1_clk1m # !C1L841 & !C1L603);
C1_clk1m = DFFEAS(C1_clk1m_lut_out, C1_clk1s, VCC, , , , , , );


--U72L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is arithmetic

U72L2_carry_eqn = U72L6;
U72L2 = U72L2_carry_eqn $ (!EB5L01 & !EB5L9);

--U72L3 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~43
--operation mode is arithmetic

U72L3 = CARRY(!U72L6 & (EB5L01 # EB5L9));


--T11L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T11L2_carry_eqn = T11L4;
T11L2 = T11L2_carry_eqn;


--U62L2 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U62L2_carry_eqn = U62L6;
U62L2 = !U62L2_carry_eqn;


--EB5L01 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~460
--operation mode is normal

EB5L01 = !U62L2 & (T11L2 $ C1_m[3]);


--U62L3 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~46
--operation mode is arithmetic

U62L3_carry_eqn = U62L8;
U62L3 = U62L3_carry_eqn $ (!EB5L1 & !EB5L2);

--U62L4 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is arithmetic

U62L4 = CARRY(!EB5L1 & !EB5L2 & !U62L8);


--EB5L9 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~17
--operation mode is normal

EB5L9 = U62L2 & U62L3;


--U72L4 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~46
--operation mode is normal

U72L4_carry_eqn = U72L8;
U72L4 = !U72L4_carry_eqn;


--EB5L51 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[28]~461
--operation mode is normal

EB5L51 = U72L4 & U72L2 # !U72L4 & (EB5L01 # EB5L9);


--EB5L31 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[26]~462
--operation mode is normal

EB5L31 = U72L4 $ C1_m[1];


--U72L5 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

U72L5_carry_eqn = U72L01;
U72L5 = U72L5_carry_eqn $ (!EB5L7 & !EB5L8);

--U72L6 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

U72L6 = CARRY(!EB5L7 & !EB5L8 & !U72L01);


--EB5L41 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[27]~463
--operation mode is normal

EB5L41 = U72L4 & U72L5 # !U72L4 & (U62L2 $ C1_m[2]);


--C1L97 is clock:inst1|add~4165
--operation mode is normal

C1L97_carry_eqn = C1L49;
C1L97 = C1_m[5] $ (C1L97_carry_eqn);


--C1L08 is clock:inst1|add~4170
--operation mode is normal

C1L08_carry_eqn = C1L69;
C1L08 = C1_m[5] $ (!C1L08_carry_eqn);


--C1L21 is clock:inst1|LessThan~1397
--operation mode is normal

C1L21 = !C1_m[1] & !C1_m[2];


--C1L31 is clock:inst1|LessThan~1398
--operation mode is normal

C1L31 = !C1_m[4] & !C1_m[5];


--C1L41 is clock:inst1|LessThan~1399
--operation mode is normal

C1L41 = C1_m[3] # C1_m[0] # !C1L31 # !C1L21;


--C1L973 is clock:inst1|m~1044
--operation mode is normal

C1L973 = C1_num # C1L41 & (!C1_pos[0]);


--C1L51 is clock:inst1|LessThan~1400
--operation mode is normal

C1L51 = C1_m[4] # C1_m[5] # C1_m[3] & !C1L21;


--C1L083 is clock:inst1|m~1045
--operation mode is normal

C1L083 = C1_num # C1_pos[0] & C1L51;


--C1L183 is clock:inst1|m~1046
--operation mode is normal

C1L183 = C1L973 & (C1L083 & (C1L87) # !C1L083 & C1L08) # !C1L973 & (!C1L083);


--C1L283 is clock:inst1|m~1047
--operation mode is normal

C1L283 = C1L762 & (C1L183 & !C1L332 # !C1L183 & (C1L97)) # !C1L762 & (C1L183);


--C1L383 is clock:inst1|m~1048
--operation mode is normal

C1L383 = C1_pos[1] & C1_m[5] # !C1_pos[1] & (C1L283 & !C1L862);


--C1L18 is clock:inst1|add~4175
--operation mode is normal

C1L18_carry_eqn = C1L89;
C1L18 = C1_m[5] $ (!C1L18_carry_eqn);


--C1L61 is clock:inst1|LessThan~1401
--operation mode is normal

C1L61 = C1_m[4] & C1_m[5];


--C1L483 is clock:inst1|m~1049
--operation mode is normal

C1L483 = C1L862 & (C1L21 & !C1_m[3] # !C1L61);


--C1L583 is clock:inst1|m~1050
--operation mode is normal

C1L583 = C1L383 # C1L18 & C1L483 & !C1_pos[1];


--C1L28 is clock:inst1|add~4180
--operation mode is arithmetic

C1L28_carry_eqn = C1L561;
C1L28 = C1_alm_m[4] $ (C1L28_carry_eqn);

--C1L38 is clock:inst1|add~4182
--operation mode is arithmetic

C1L38 = CARRY(!C1L561 # !C1_alm_m[4]);


--C1L48 is clock:inst1|add~4185
--operation mode is arithmetic

C1L48_carry_eqn = C1L761;
C1L48 = C1_alm_m[4] $ (!C1L48_carry_eqn);

--C1L58 is clock:inst1|add~4187