digtalclk.map.eqn

用Altera公司的QuartusII编写的电子钟程序

--operation mode is normal

C1_disp[11]_lut_out = C1L25 & (!C1_clk1s # !C1L123);
C1_disp[11] = DFFEAS(C1_disp[11]_lut_out, J1_modulus_trigger, VCC, , C1L223, , , , );


--C1_disp[15] is clock:inst1|disp[15]
--operation mode is normal

C1_disp[15]_lut_out = !C1L35 & (U16L4 & U16L7 # !U16L4 & (C1L45));
C1_disp[15] = DFFEAS(C1_disp[15]_lut_out, J1_modulus_trigger, VCC, , C1L233, , , , );


--ZB1L7 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result95w~44
--operation mode is normal

ZB1L7 = J1_safe_q[17] & (J1_safe_q[16]) # !J1_safe_q[17] & (J1_safe_q[16] & C1_disp[11] # !J1_safe_q[16] & (C1_disp[15]));


--C1_disp[3] is clock:inst1|disp[3]
--operation mode is normal

C1_disp[3]_lut_out = C1L65 & (!C1_clk1s # !C1L123);
C1_disp[3] = DFFEAS(C1_disp[3]_lut_out, J1_modulus_trigger, VCC, , C1L213, , , , );


--ZB1L8 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result95w~45
--operation mode is normal

ZB1L8 = J1_safe_q[17] & (ZB1L7 & (C1_disp[3]) # !ZB1L7 & C1_disp[7]) # !J1_safe_q[17] & (ZB1L7);


--G1L7 is bin2seg:inst9|data_out[6]~72
--operation mode is normal

G1L7 = ZB1L8 # ZB1L4 & (!ZB1L6 # !ZB1L2) # !ZB1L4 & (ZB1L6);


--G1L6 is bin2seg:inst9|data_out[5]~73
--operation mode is normal

G1L6 = ZB1L4 & !ZB1L8 & (ZB1L2 # !ZB1L6) # !ZB1L4 & (ZB1L6 & (ZB1L8) # !ZB1L6 & ZB1L2 & !ZB1L8);


--G1L5 is bin2seg:inst9|data_out[4]~74
--operation mode is normal

G1L5 = ZB1L4 & ZB1L2 & (!ZB1L8) # !ZB1L4 & (ZB1L6 & (!ZB1L8) # !ZB1L6 & ZB1L2);


--G1L4 is bin2seg:inst9|data_out[3]~75
--operation mode is normal

G1L4 = ZB1L2 & (ZB1L4 $ !ZB1L6) # !ZB1L2 & (ZB1L4 & !ZB1L6 & ZB1L8 # !ZB1L4 & ZB1L6 & !ZB1L8);


--G1L3 is bin2seg:inst9|data_out[2]~76
--operation mode is normal

G1L3 = ZB1L6 & ZB1L8 & (ZB1L4 # !ZB1L2) # !ZB1L6 & !ZB1L2 & ZB1L4 & !ZB1L8;


--G1L2 is bin2seg:inst9|data_out[1]~77
--operation mode is normal

G1L2 = ZB1L4 & (ZB1L2 & (ZB1L8) # !ZB1L2 & ZB1L6) # !ZB1L4 & ZB1L6 & (ZB1L2 $ ZB1L8);


--G1L1 is bin2seg:inst9|data_out[0]~78
--operation mode is normal

G1L1 = ZB1L6 & (ZB1L8 & (!ZB1L4) # !ZB1L8 & !ZB1L2) # !ZB1L6 & ZB1L2 & (ZB1L4 $ !ZB1L8);


--C1L75 is clock:inst1|add~4111
--operation mode is normal

C1L75_carry_eqn = C1L38;
C1L75 = C1_alm_m[5] $ (!C1L75_carry_eqn);


--U52L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~41
--operation mode is arithmetic

U52L2_carry_eqn = U52L6;
U52L2 = U52L2_carry_eqn $ (!EB4L01 & !EB4L9);

--U52L3 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~43
--operation mode is arithmetic

U52L3 = CARRY(!U52L6 & (EB4L01 # EB4L9));


--T01L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T01L2_carry_eqn = T01L4;
T01L2 = T01L2_carry_eqn;


--U42L2 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~41
--operation mode is normal

U42L2_carry_eqn = U42L6;
U42L2 = !U42L2_carry_eqn;


--EB4L01 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~467
--operation mode is normal

EB4L01 = !U42L2 & (T01L2 $ C1_alm_m[3]);


--U42L3 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~46
--operation mode is arithmetic

U42L3_carry_eqn = U42L8;
U42L3 = U42L3_carry_eqn $ (!EB4L1 & !EB4L2);

--U42L4 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is arithmetic

U42L4 = CARRY(!EB4L1 & !EB4L2 & !U42L8);


--EB4L9 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[22]~17
--operation mode is normal

EB4L9 = U42L2 & U42L3;


--U52L4 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~46
--operation mode is normal

U52L4_carry_eqn = U52L8;
U52L4 = !U52L4_carry_eqn;


--EB4L51 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[28]~468
--operation mode is normal

EB4L51 = U52L4 & U52L2 # !U52L4 & (EB4L01 # EB4L9);


--U52L5 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~51
--operation mode is arithmetic

U52L5_carry_eqn = U52L01;
U52L5 = U52L5_carry_eqn $ (!EB4L7 & !EB4L8);

--U52L6 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53
--operation mode is arithmetic

U52L6 = CARRY(!EB4L7 & !EB4L8 & !U52L01);


--EB4L41 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|StageOut[27]~469
--operation mode is normal

EB4L41 = U52L4 & U52L5 # !U52L4 & (U42L2 $ C1_alm_m[2]);


--C1L85 is clock:inst1|add~4116
--operation mode is normal

C1L85 = EB4L41 & (U52L4 $ C1_alm_m[1]);


--C1L95 is clock:inst1|add~4117
--operation mode is normal

C1L95_carry_eqn = C1L58;
C1L95 = C1_alm_m[5] $ (C1L95_carry_eqn);


--C1_pos[0] is clock:inst1|pos[0]
--operation mode is normal

C1_pos[0]_lut_out = !C1L421;
C1_pos[0] = DFFEAS(C1_pos[0]_lut_out, J1_modulus_trigger, VCC, , C1L123, , , , );


--C1_num is clock:inst1|num
--operation mode is normal

C1_num_lut_out = C1_num & (C1L214 # C1_lastkey3 & !D3_keyout) # !C1_num & (C1_lastkey3 & !D3_keyout);
C1_num = DFFEAS(C1_num_lut_out, J1_modulus_trigger, VCC, , C1L123, , , , );


--C1L762 is clock:inst1|alm_m[1]~1249
--operation mode is normal

C1L762 = C1_pos[0] & (!C1_num);


--C1L06 is clock:inst1|add~4122
--operation mode is normal

C1L06_carry_eqn = C1L78;
C1L06 = C1_alm_m[5] $ (!C1L06_carry_eqn);


--C1L16 is clock:inst1|add~4127
--operation mode is normal

C1L16_carry_eqn = C1L98;
C1L16 = C1_alm_m[5] $ (C1L16_carry_eqn);


--C1L3 is clock:inst1|LessThan~1386
--operation mode is normal

C1L3 = !C1_alm_m[1] & !C1_alm_m[3] & !C1_alm_m[2];


--C1L4 is clock:inst1|LessThan~1387
--operation mode is normal

C1L4 = !C1_alm_m[4] & !C1_alm_m[5];


--C1L772 is clock:inst1|alm_m[5]~1250
--operation mode is normal

C1L772 = C1_num # C1L52 & (!C1_pos[0]);


--C1L5 is clock:inst1|LessThan~1388
--operation mode is normal

C1L5 = C1_alm_m[3] & (C1_alm_m[1] # C1_alm_m[2]) # !C1L4;


--C1L872 is clock:inst1|alm_m[5]~1251
--operation mode is normal

C1L872 = C1_num # C1_pos[0] & C1L5;


--C1L182 is clock:inst1|alm_m~1252
--operation mode is normal

C1L182 = C1L772 & (C1L872 & (C1L16) # !C1L872 & C1L06) # !C1L772 & (!C1L872);


--C1L282 is clock:inst1|alm_m~1253
--operation mode is normal

C1L282 = C1L762 & (C1L182 & !C1L132 # !C1L182 & (C1L95)) # !C1L762 & (C1L182);


--C1L862 is clock:inst1|alm_m[1]~1254
--operation mode is normal

C1L862 = C1_pos[0] & C1_num;


--C1L6 is clock:inst1|LessThan~1389
--operation mode is normal

C1L6 = C1_alm_m[2] # C1_alm_m[1] & C1_alm_m[0];


--C1L7 is clock:inst1|LessThan~1390
--operation mode is normal

C1L7 = C1_alm_m[4] & C1_alm_m[5] & C1_alm_m[3] & C1L6;


--C1L972 is clock:inst1|alm_m[5]~1255
--operation mode is normal

C1L972 = C1_num & C1L7 & (!C1_pos[0]);


--C1L8 is clock:inst1|LessThan~1391
--operation mode is normal

C1L8 = C1_alm_m[4] & C1_alm_m[5];


--C1L082 is clock:inst1|alm_m[5]~1256
--operation mode is normal

C1L082 = C1L972 # C1L862 & C1L8 & !C1L3;


--J1_modulus_trigger is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|modulus_trigger
--operation mode is normal

J1_modulus_trigger_carry_eqn = J1L54;
J1_modulus_trigger = J1L1 # J1_modulus_trigger_carry_eqn;


--C1_pos[1] is clock:inst1|pos[1]
--operation mode is normal

C1_pos[1]_lut_out = C1L521;
C1_pos[1] = DFFEAS(C1_pos[1]_lut_out, J1_modulus_trigger, VCC, , C1L123, , , , );


--C1_alm_set is clock:inst1|alm_set
--operation mode is normal

C1_alm_set_lut_out = C1L424;
C1_alm_set = DFFEAS(C1_alm_set_lut_out, J1_modulus_trigger, VCC, , C1L1, , , , );


--C1_lastas is clock:inst1|lastas
--operation mode is normal

C1_lastas_lut_out = C1_alm_set;
C1_lastas = DFFEAS(C1_lastas_lut_out, J1_modulus_trigger, VCC, , , , , , );


--C1L672 is clock:inst1|alm_m[5]~42
--operation mode is normal

C1L672 = !C1_pos[1] & !C1_alm_set & (C1_lastas);


--U82L2 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~43
--operation mode is arithmetic

U82L2_carry_eqn = U82L6;
U82L2 = U82L2_carry_eqn $ (!LB3L3 & !LB3L4);

--U82L3 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~45
--operation mode is arithmetic

U82L3 = CARRY(!U82L6 & (LB3L3 # LB3L4));


--T21L2 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~32
--operation mode is normal

T21L2_carry_eqn = T21L6;
T21L2 = T21L2_carry_eqn;


--T21L3 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~37
--operation mode is arithmetic

T21L3_carry_eqn = T21L8;
T21L3 = C1_alm_h[3] $ (!T21L3_carry_eqn);

--T21L4 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[2]~39
--operation mode is arithmetic

T21L4 = CARRY(!C1_alm_h[3] & (!T21L8));


--LB3L4 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[17]~17
--operation mode is normal

LB3L4 = T21L2 & T21L3;


--LB3L3 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[17]~12
--operation mode is normal

LB3L3 = C1_alm_h[3] & (!T21L2);


--U82L4 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48
--operation mode is normal

U82L4_carry_eqn = U82L8;
U82L4 = !U82L4_carry_eqn;


--LB3L9 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[23]~310
--operation mode is normal

LB3L9 = U82L4 & U82L2 # !U82L4 & (LB3L4 # LB3L3);


--U82L5 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~53
--operation mode is arithmetic

U82L5_carry_eqn = U82L01;
U82L5 = U82L5_carry_eqn $ (!LB3L1 & !LB3L2);

--U82L6 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~55
--operation mode is arithmetic

U82L6 = CARRY(!LB3L1 & !LB3L2 & !U82L01);


--LB3L8 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|StageOut[22]~311
--operation mode is normal

LB3L8 = U82L4 & U82L5 # !U82L4 & (T21L2 $ C1_alm_h[2]);


--C1L26 is clock:inst1|add~4132
--operation mode is normal

C1L26 = LB3L8 & (U82L4 $ C1_alm_h[1]);


--C1L36 is clock:inst1|add~4133
--operation mode is normal

C1L36 = C1_alm_h[3] $ (C1_alm_h[1] # C1_alm_h[2]);


--C1L9 is clock:inst1|LessThan~1392
--operation mode is normal

C1L9 = !C1_alm_h[4] & (!C1_alm_h[1] & !C1_alm_h[2] # !C1_alm_h[3]);


--C1L742 is clock:inst1|alm_h~1813
--operation mode is normal

C1L742 = C1L9 & (LB3L9 $ !C1L26) # !C1L9 & (C1L36);


--C1L46 is clock:inst1|add~4134
--operation mode is normal

C1L46 = C1_alm_h[3] $ (C1_alm_h[1] & C1_alm_h[2]);


--C1L56 is clock:inst1|add~4135
--operation mode is arithmetic

C1L56_carry_eqn = C1L721;
C1L56 = C1_alm_h[3] $ (!C1L56_carry_eqn);

--C1L66 is clock:inst1|add~4137
--operation mode is arithmetic

C1L66 = CARRY(!C1_alm_h[3] & (!C1L721));


--C1L76 is clock:inst1|add~4140
--operation mode is arithmetic

C1L76_carry_eqn = C1L921;
C1L76 = C1_alm_h[3] $ (C1L76_carry_eqn);

--C1L86 is clock:inst1|add~4142
--operation mode is arithmetic

C1L86 = CARRY(!C1L921 # !C1_alm_h[3]);


--C1L142 is clock:inst1|alm_h[3]~1814
--operation mode is normal

C1L142 = C1_alm_h[3] # C1_alm_h[0] # C1_alm_h[1] # C1_alm_h[2];


--C1L242 is clock:inst1|alm_h[3]~1815