digtalclk.map.eqn

用Altera公司的QuartusII编写的电子钟程序

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--C1_alm_m[5] is clock:inst1|alm_m[5]
--operation mode is normal

C1_alm_m[5]_lut_out = !C1L082 & (C1L862 & C1L75 # !C1L862 & (C1L282));
C1_alm_m[5] = DFFEAS(C1_alm_m[5]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , , );


--C1_alm_h[3] is clock:inst1|alm_h[3]
--operation mode is normal

C1_alm_h[3]_lut_out = C1L442 & (C1L762 & C1L742 # !C1L762 & (C1L942));
C1_alm_h[3] = DFFEAS(C1_alm_h[3]_lut_out, J1_modulus_trigger, VCC, , C1L642, , , , );


--C1_h[3] is clock:inst1|h[3]
--operation mode is normal

C1_h[3]_lut_out = C1L17;
C1_h[3] = DFFEAS(C1_h[3]_lut_out, C1_clk1h, VCC, , , C1L153, !C1_set, , );


--C1_m[5] is clock:inst1|m[5]
--operation mode is normal

C1_m[5]_lut_out = C1L87;
C1_m[5] = DFFEAS(C1_m[5]_lut_out, C1_clk1m, VCC, , , C1L583, !C1_set, , );


--A1L8 is inst2~78
--operation mode is normal

A1L8 = C1_alm_m[5] & C1_m[5] & (C1_alm_h[3] $ !C1_h[3]) # !C1_alm_m[5] & !C1_m[5] & (C1_alm_h[3] $ !C1_h[3]);


--C1_alm_m[1] is clock:inst1|alm_m[1]
--operation mode is arithmetic

C1_alm_m[1]_lut_out = C1L792;
C1_alm_m[1] = DFFEAS(C1_alm_m[1]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , !C1L072, );

--U52L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

U52L1 = CARRY(C1_alm_m[1]);


--C1_m[1] is clock:inst1|m[1]
--operation mode is arithmetic

C1_m[1]_lut_out = C1L431;
C1_m[1] = DFFEAS(C1_m[1]_lut_out, C1_clk1m, VCC, , , C1L793, !C1_set, , );

--U72L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_5|add_sub_cella[1]~COUT
--operation mode is arithmetic

U72L1 = CARRY(C1_m[1]);


--C1_alm_m[4] is clock:inst1|alm_m[4]
--operation mode is normal

C1_alm_m[4]_lut_out = !C1L082 & (C1L862 & C1L28 # !C1L862 & (C1L482));
C1_alm_m[4] = DFFEAS(C1_alm_m[4]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , , );


--C1_m[4] is clock:inst1|m[4]
--operation mode is normal

C1_m[4]_lut_out = C1L29;
C1_m[4] = DFFEAS(C1_m[4]_lut_out, C1_clk1m, VCC, , , C1L983, !C1_set, , );


--C1L524 is clock:inst1|spk~4
--operation mode is normal

C1L524 = C1_alm_m[4] $ C1_m[4];


--A1L9 is inst2~79
--operation mode is normal

A1L9 = A1L8 & !C1L524 & (C1_alm_m[1] $ !C1_m[1]);


--C1_alm_m[3] is clock:inst1|alm_m[3]
--operation mode is arithmetic

C1_alm_m[3]_lut_out = C1L892;
C1_alm_m[3] = DFFEAS(C1_alm_m[3]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , !C1L072, );

--T01L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

T01L1 = CARRY(C1_alm_m[3]);


--C1_alm_h[0] is clock:inst1|alm_h[0]
--operation mode is normal

C1_alm_h[0]_lut_out = C1_pos[0] & C1_alm_h[0] # !C1_pos[0] & (C1L152);
C1_alm_h[0] = DFFEAS(C1_alm_h[0]_lut_out, J1_modulus_trigger, VCC, , C1L642, , , , );


--C1_h[0] is clock:inst1|h[0]
--operation mode is normal

C1_h[0]_lut_out = C1L501;
C1_h[0] = DFFEAS(C1_h[0]_lut_out, C1_clk1h, VCC, , , C1L353, !C1_set, , );


--C1_m[3] is clock:inst1|m[3]
--operation mode is arithmetic

C1_m[3]_lut_out = C1L731;
C1_m[3] = DFFEAS(C1_m[3]_lut_out, C1_clk1m, VCC, , , C1L104, !C1_set, , );

--T11L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

T11L1 = CARRY(C1_m[3]);


--A1L01 is inst2~80
--operation mode is normal

A1L01 = C1_alm_m[3] & C1_m[3] & (C1_alm_h[0] $ !C1_h[0]) # !C1_alm_m[3] & !C1_m[3] & (C1_alm_h[0] $ !C1_h[0]);


--C1_alm_h[1] is clock:inst1|alm_h[1]
--operation mode is arithmetic

C1_alm_h[1]_lut_out = C1L852;
C1_alm_h[1] = DFFEAS(C1_alm_h[1]_lut_out, J1_modulus_trigger, VCC, , C1L642, , , !C1L442, );

--U82L1 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

U82L1 = CARRY(C1_alm_h[1]);


--C1_alm_m[0] is clock:inst1|alm_m[0]
--operation mode is normal

C1_alm_m[0]_lut_out = C1_pos[0] & C1_alm_m[0] # !C1_pos[0] & (C1L782);
C1_alm_m[0] = DFFEAS(C1_alm_m[0]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , , );


--C1_m[0] is clock:inst1|m[0]
--operation mode is normal

C1_m[0]_lut_out = C1L411;
C1_m[0] = DFFEAS(C1_m[0]_lut_out, C1_clk1m, VCC, , , C1L193, !C1_set, , );


--C1_h[1] is clock:inst1|h[1]
--operation mode is arithmetic

C1_h[1]_lut_out = C1L081;
C1_h[1] = DFFEAS(C1_h[1]_lut_out, C1_clk1h, VCC, , , C1L163, !C1_set, , );

--U92L1 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

U92L1 = CARRY(C1_h[1]);


--A1L11 is inst2~81
--operation mode is normal

A1L11 = C1_alm_h[1] & C1_h[1] & (C1_alm_m[0] $ !C1_m[0]) # !C1_alm_h[1] & !C1_h[1] & (C1_alm_m[0] $ !C1_m[0]);


--J1_safe_q[15] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[15]
--operation mode is arithmetic

J1_safe_q[15]_carry_eqn = J1L73;
J1_safe_q[15]_lut_out = J1_safe_q[15] $ (J1_safe_q[15]_carry_eqn);
J1_safe_q[15] = DFFEAS(J1_safe_q[15]_lut_out, clk50mhz, VCC, , , ~GND, , , J1_modulus_trigger);

--J1L93 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella15~COUT
--operation mode is arithmetic

J1L93 = CARRY(!J1L73 # !J1_safe_q[15]);


--C1_alm_h[4] is clock:inst1|alm_h[4]
--operation mode is normal

C1_alm_h[4]_lut_out = C1_pos[0] & (C1L352 & C1L452 & !C1L552 # !C1L352 & (C1L552)) # !C1_pos[0] & C1L352;
C1_alm_h[4] = DFFEAS(C1_alm_h[4]_lut_out, J1_modulus_trigger, VCC, , C1L642, , , , );


--C1_alm_h[2] is clock:inst1|alm_h[2]
--operation mode is arithmetic

C1_alm_h[2]_lut_out = C1L362;
C1_alm_h[2] = DFFEAS(C1_alm_h[2]_lut_out, J1_modulus_trigger, VCC, , C1L642, , , !C1L442, );

--T21L1 is clock:inst1|lpm_divide:mod_rtl_2|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

T21L1 = CARRY(C1_alm_h[2]);


--C1_h[2] is clock:inst1|h[2]
--operation mode is arithmetic

C1_h[2]_lut_out = C1L381;
C1_h[2] = DFFEAS(C1_h[2]_lut_out, C1_clk1h, VCC, , , C1L563, !C1_set, , );

--T31L1 is clock:inst1|lpm_divide:mod_rtl_3|lpm_divide_kdf:auto_generated|sign_div_unsign_jhg:divider|alt_u_div_bld:divider|add_sub_ne8:add_sub_3|add_sub_cella[1]~COUT
--operation mode is arithmetic

T31L1 = CARRY(C1_h[2]);


--C1_h[4] is clock:inst1|h[4]
--operation mode is normal

C1_h[4]_lut_out = C1L021;
C1_h[4] = DFFEAS(C1_h[4]_lut_out, C1_clk1h, VCC, , , C1L853, !C1_set, , );


--A1L21 is inst2~82
--operation mode is normal

A1L21 = C1_alm_h[4] & C1_h[4] & (C1_alm_h[2] $ !C1_h[2]) # !C1_alm_h[4] & !C1_h[4] & (C1_alm_h[2] $ !C1_h[2]);


--C1_alm_m[2] is clock:inst1|alm_m[2]
--operation mode is arithmetic

C1_alm_m[2]_lut_out = C1L992;
C1_alm_m[2] = DFFEAS(C1_alm_m[2]_lut_out, J1_modulus_trigger, VCC, , C1L672, , , !C1L072, );

--U42L1 is clock:inst1|lpm_divide:mod_rtl_0|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

U42L1 = CARRY(C1_alm_m[2]);


--C1_m[2] is clock:inst1|m[2]
--operation mode is arithmetic

C1_m[2]_lut_out = C1L041;
C1_m[2] = DFFEAS(C1_m[2]_lut_out, C1_clk1m, VCC, , , C1L504, !C1_set, , );

--U62L1 is clock:inst1|lpm_divide:mod_rtl_1|lpm_divide_ldf:auto_generated|sign_div_unsign_khg:divider|alt_u_div_dld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT
--operation mode is arithmetic

U62L1 = CARRY(C1_m[2]);


--A1L31 is inst2~83
--operation mode is normal

A1L31 = J1_safe_q[15] & A1L21 & (C1_alm_m[2] $ !C1_m[2]);


--inst2 is inst2
--operation mode is normal

inst2 = A1L9 & A1L01 & A1L11 & A1L31;


--J1_safe_q[16] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[16]
--operation mode is arithmetic

J1_safe_q[16]_carry_eqn = J1L93;
J1_safe_q[16]_lut_out = J1_safe_q[16] $ (!J1_safe_q[16]_carry_eqn);
J1_safe_q[16] = DFFEAS(J1_safe_q[16]_lut_out, clk50mhz, VCC, , , ~GND, , , J1_modulus_trigger);

--J1L14 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella16~COUT
--operation mode is arithmetic

J1L14 = CARRY(J1_safe_q[16] & (!J1L93));


--J1_safe_q[17] is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|safe_q[17]
--operation mode is arithmetic

J1_safe_q[17]_carry_eqn = J1L14;
J1_safe_q[17]_lut_out = J1_safe_q[17] $ (J1_safe_q[17]_carry_eqn);
J1_safe_q[17] = DFFEAS(J1_safe_q[17]_lut_out, clk50mhz, VCC, , , ~GND, , , J1_modulus_trigger);

--J1L34 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|counter_cella17~COUT
--operation mode is arithmetic

J1L34 = CARRY(!J1L14 # !J1_safe_q[17]);


--J1L2 is lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_gu8:auto_generated|cmpr1_aeb_int~137
--operation mode is normal

J1L2 = J1_safe_q[16] & J1_safe_q[17];


--BC1L3 is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode24w[2]~34
--operation mode is normal

BC1L3 = J1_safe_q[17] & (!J1_safe_q[16]);


--BC1L4 is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode24w[2]~35
--operation mode is normal

BC1L4 = J1_safe_q[16] & (!J1_safe_q[17]);


--BC1_w_anode1w[2] is lpm_decode0:inst8|lpm_decode:lpm_decode_component|decode_m0b:auto_generated|w_anode1w[2]
--operation mode is normal

BC1_w_anode1w[2] = J1_safe_q[16] # J1_safe_q[17];


--C1_disp[8] is clock:inst1|disp[8]
--operation mode is normal

C1_disp[8]_lut_out = C1L72 & (!C1_clk1s # !C1L123);
C1_disp[8] = DFFEAS(C1_disp[8]_lut_out, J1_modulus_trigger, VCC, , C1L223, , , , );


--C1_disp[4] is clock:inst1|disp[4]
--operation mode is normal

C1_disp[4]_lut_out = C1L92 & (!C1_clk1s # !C1L123);
C1_disp[4] = DFFEAS(C1_disp[4]_lut_out, J1_modulus_trigger, VCC, , C1L813, , , , );


--C1_disp[12] is clock:inst1|disp[12]
--operation mode is normal

C1_disp[12]_lut_out = C1L13 & (!C1_clk1s # !C1L123);
C1_disp[12] = DFFEAS(C1_disp[12]_lut_out, J1_modulus_trigger, VCC, , C1L233, , , , );


--ZB1L1 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result15w~44
--operation mode is normal

ZB1L1 = J1_safe_q[16] & (J1_safe_q[17]) # !J1_safe_q[16] & (J1_safe_q[17] & C1_disp[4] # !J1_safe_q[17] & (C1_disp[12]));


--C1_disp[0] is clock:inst1|disp[0]
--operation mode is normal

C1_disp[0]_lut_out = C1L33 & (!C1_clk1s # !C1L123);
C1_disp[0] = DFFEAS(C1_disp[0]_lut_out, J1_modulus_trigger, VCC, , C1L213, , , , );


--ZB1L2 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result15w~45
--operation mode is normal

ZB1L2 = J1_safe_q[16] & (ZB1L1 & (C1_disp[0]) # !ZB1L1 & C1_disp[8]) # !J1_safe_q[16] & (ZB1L1);


--C1_disp[5] is clock:inst1|disp[5]
--operation mode is normal

C1_disp[5]_lut_out = C1L53 & (!C1_clk1s # !C1L123);
C1_disp[5] = DFFEAS(C1_disp[5]_lut_out, J1_modulus_trigger, VCC, , C1L813, , , , );


--C1_disp[9] is clock:inst1|disp[9]
--operation mode is normal

C1_disp[9]_lut_out = C1L73 & (!C1_clk1s # !C1L123);
C1_disp[9] = DFFEAS(C1_disp[9]_lut_out, J1_modulus_trigger, VCC, , C1L223, , , , );


--C1_disp[13] is clock:inst1|disp[13]
--operation mode is normal

C1_disp[13]_lut_out = C1L93 & (!C1_clk1s # !C1L123);
C1_disp[13] = DFFEAS(C1_disp[13]_lut_out, J1_modulus_trigger, VCC, , C1L233, , , , );


--ZB1L3 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result45w~44
--operation mode is normal

ZB1L3 = J1_safe_q[17] & (J1_safe_q[16]) # !J1_safe_q[17] & (J1_safe_q[16] & C1_disp[9] # !J1_safe_q[16] & (C1_disp[13]));


--C1_disp[1] is clock:inst1|disp[1]
--operation mode is normal

C1_disp[1]_lut_out = C1L14 & (!C1_clk1s # !C1L123);
C1_disp[1] = DFFEAS(C1_disp[1]_lut_out, J1_modulus_trigger, VCC, , C1L213, , , , );


--ZB1L4 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result45w~45
--operation mode is normal

ZB1L4 = J1_safe_q[17] & (ZB1L3 & (C1_disp[1]) # !ZB1L3 & C1_disp[5]) # !J1_safe_q[17] & (ZB1L3);


--C1_disp[10] is clock:inst1|disp[10]
--operation mode is normal

C1_disp[10]_lut_out = C1L34 & (!C1_clk1s # !C1L123);
C1_disp[10] = DFFEAS(C1_disp[10]_lut_out, J1_modulus_trigger, VCC, , C1L223, , , , );


--C1_disp[6] is clock:inst1|disp[6]
--operation mode is normal

C1_disp[6]_lut_out = C1L54 & (!C1_clk1s # !C1L123);
C1_disp[6] = DFFEAS(C1_disp[6]_lut_out, J1_modulus_trigger, VCC, , C1L813, , , , );


--C1_disp[14] is clock:inst1|disp[14]
--operation mode is normal

C1_disp[14]_lut_out = C1L64 & (!C1_clk1s # !C1L123);
C1_disp[14] = DFFEAS(C1_disp[14]_lut_out, J1_modulus_trigger, VCC, , C1L233, , , , );


--ZB1L5 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result70w~44
--operation mode is normal

ZB1L5 = J1_safe_q[16] & (J1_safe_q[17]) # !J1_safe_q[16] & (J1_safe_q[17] & C1_disp[6] # !J1_safe_q[17] & (C1_disp[14]));


--C1_disp[2] is clock:inst1|disp[2]
--operation mode is normal

C1_disp[2]_lut_out = C1L84 & (!C1_clk1s # !C1L123);
C1_disp[2] = DFFEAS(C1_disp[2]_lut_out, J1_modulus_trigger, VCC, , C1L213, , , , );


--ZB1L6 is lpm_mux0:inst7|lpm_mux:lpm_mux_component|mux_9fc:auto_generated|w_result70w~45
--operation mode is normal

ZB1L6 = J1_safe_q[16] & (ZB1L5 & (C1_disp[2]) # !ZB1L5 & C1_disp[10]) # !J1_safe_q[16] & (ZB1L5);


--C1_disp[7] is clock:inst1|disp[7]
--operation mode is normal

C1_disp[7]_lut_out = C1L05 & (!C1_clk1s # !C1L123);
C1_disp[7] = DFFEAS(C1_disp[7]_lut_out, J1_modulus_trigger, VCC, , C1L813, , , , );


--C1_disp[11] is clock:inst1|disp[11]