📄 start_gcc.s
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/*
* file:
* start.S
* description:
* s3c2410 startup code.
*/
/* MEMORY AREA */
#define _RAM_STARTADDRESS 0x30000000
#define _RAM_ENDADDRESS 0x34000000
#define _ROM_STARTADDRESS 0x00000000
#define _ROM_ENDADDRESS 0x00200000
/* STACK DEFINITIONS */
#define _FIQ_STACK_ADDRESS (_RAM_ENDADDRESS-0x08000) /* 14K */
#define _IRQ_STACK_ADDRESS (_RAM_ENDADDRESS-0x0b800) /* 14K */
#define _ABT_STACK_ADDRESS (_RAM_ENDADDRESS-0x0f000) /* 1K */
#define _SVC_STACK_ADDRESS (_RAM_ENDADDRESS-0x0f400) /* 2K */
#define _UND_STACK_ADDRESS (_RAM_ENDADDRESS-0x0fc00) /* 1k */
#define _USR_STACK_ADDRESS (_RAM_ENDADDRESS-0x10000) /* 0k */
/* PROCESSOR MODE */
#define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */
#define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */
#define ABT_MODE 0x17 /* Abort Mode(ABT) */
#define SVC_MODE 0x13 /* Supervisor Mode (SVC) */
#define UND_MODE 0x1b /* Undefine Mode(UDF) */
#define USR_MODE 0x10 /* User Mode(USR) */
#define SYS_MODE 0x1f /* System Mode(SYS) */
#define MODE_MSK 0x1f /* Processor Mode Mask */
/* IRQ BITS */
#define F_BIT 0x40 /* FIQ Disable */
#define I_BIT 0x80 /* IRQ Disable */
#define LOCKOUT 0xc0 /* Interrupt lockout mask value */
/* watchdog controller */
#define WTCON 0x53000000
#define WTDAT 0x53000004
#define WTCNT 0x53000008
/* interrupt controller */
#define SRCPND 0x4a000000
#define INTMOD 0x4a000004
#define INTMSK 0x4a000008
#define PRIORITY 0x4a00000c
#define INTPND 0x4a000010
#define INTOFFSET 0x4a000014
#define SUBSRCPND 0x4a000018
#define INTSUBMSK 0x4a00001c
/* clock controller */
#define LOCKTIME 0x4c000000
#define MPLLCON 0x4c000004
#define UPLLCON 0x4c000008
#define CLKCON 0x4c00000c
#define CLKSLOW 0x4c000010
#define CLKDIVN 0x4c000014
#define MM_DIV 0xa1 /* Fin=12MHz Fout=202.8MHz */
#define MP_DIV 0x03
#define MS_DIV 0x01
#define UM_DIV 0x78
#define UP_DIV 0x02
#define US_DIV 0x03
/* memory controller */
#define BWSCON 0x48000000
#define BANKCON0 0x48000004
#define BANKCON1 0x48000008
#define BANKCON2 0x4800000c
#define BANKCON3 0x48000010
#define BANKCON4 0x48000014
#define BANKCON5 0x48000018
#define BANKCON6 0x4800001c
#define BANKCON7 0x48000020
#define REFRESH 0x48000024
#define BANKSIZE 0x48000028
#define MRSRB6 0x4800002c
#define MRSRB7 0x48000030
/* STARTUP CODE */
.text
.global _start
_start:
b SystemResetHandler
ldr pc, =_RAM_STARTADDRESS+4 /* b SystemUndefinedHandler */
ldr pc, =_RAM_STARTADDRESS+8 /* b SystemSwiHandler */
ldr pc, =_RAM_STARTADDRESS+12 /* b SystemPrefetchHandler */
ldr pc, =_RAM_STARTADDRESS+16 /* b SystemAbortHandler */
ldr pc, =_RAM_STARTADDRESS+20 /* b SystemReservedHandler */
ldr pc, =_RAM_STARTADDRESS+24 /* b SystemIrqHandler */
ldr pc, =_RAM_STARTADDRESS+28 /* b SystemFiqHandler */
.ltorg
ConfigMemoryData:
.word 0x22111112 /* BWSCON */
.word 0x00000600 /* BANKCON0 */
.word 0x00000700 /* BANKCON1 */
.word 0x00000700 /* BANKCON2 */
.word 0x00000700 /* BANKCON3 */
.word 0x00000700 /* BANKCON4 */
.word 0x00000700 /* BANKCON5 */
.word 0x00018001 /* BANKCON6 */
.word 0x00018001 /* BANKCON7 */
.word 0x008001e9 /* REFRESH */
.word 0x00000032 /* BANKSIZE */
.word 0x00000030 /* MRSRB6 */
.word 0x00000030 /* MRSRB7 */
SystemReservedHandler:
b SystemReservedHandler
SystemResetHandler:
ldr r0, =WTCON /* Disable WatchDog */
ldr r1, =0x8000
str r1, [r0]
ldr r0, =INTMSK /* Disable interrupt */
ldr r1, =0xffffffff
str r1, [r0]
ldr r0, =INTSUBMSK /* Disable sub interrupt */
ldr r1, =0x07ff
str r1, [r0]
ldr r0, =INTMOD /* IRQ mode */
ldr r1, =0x00
str r1, [r0]
ldr r0, =SUBSRCPND /* Clear sub interrupt pending */
ldr r1, =0x07ff
str r1, [r0]
ldr r0, =SRCPND /* Clear interrupt source */
ldr r1, =0xffffffff
str r1, [r0]
ldr r0, =INTPND /* Clear interrupt pending */
ldr r1, =0xffffffff
str r1, [r0]
b Initialize_Memory
.ltorg
Initialize_Memory:
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
ldr r0, =ConfigMemoryData
sublt r0, r0, r1
ldmia r0, {r1-r13}
ldr r0, =BWSCON
stmia r0, {r1-r13}
b Initialize_Code
.ltorg
.extern Image_RO_Base
.extern Image_RO_Limit
.extern Image_RW_Base
.extern Image_RW_Limit
.extern Image_ZI_Base
.extern Image_ZI_Limit
Initialize_Code:
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
bge Initialize_Clock
ldr r0, =_ROM_STARTADDRESS
ldr r1, =_start
ldr r2, =Image_ZI_Base
code0:
cmp r1, r2
bge code1
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
b code0
code1:
ldr pc, =_RAM_STARTADDRESS
.ltorg
Initialize_Clock:
ldr r0, =CLKDIVN
ldr r1, =0x03
str r1, [r0]
ldr r0, =LOCKTIME
ldr r1, =0x00ffffff
str r1, [r0]
ldr r0, =MPLLCON
ldr r1, =((MM_DIV<<12)+(MP_DIV<<4)+MS_DIV)
str r1, [r0]
ldr r0, =UPLLCON
ldr r1, =((UM_DIV<<12)+(UP_DIV<<4)+US_DIV)
str r1, [r0]
ldr r0, =CLKCON
ldr r1, =0x0007fff0
str r1, [r0]
ldr r0, =CLKSLOW
ldr r1, =0x04
str r1, [r0]
b Initialize_Vector
.ltorg
Initialize_Vector:
ldr r0, =_RAM_STARTADDRESS;
add r0, r0, #4
ldr r1, =SystemUndefinedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemSwiHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemPrefetchHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemAbortHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemReservedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemIrqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemFiqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
b Initialize_Stack
.ltorg
Initialize_Stack:
mov r0, #0x00
orr r1, r0, #LOCKOUT|FIQ_MODE
msr cpsr_all, r1
ldr sp, =_FIQ_STACK_ADDRESS
orr r1, r0, #I_BIT|IRQ_MODE
msr cpsr_all, r1
ldr sp, =_IRQ_STACK_ADDRESS
orr r1, r0, #LOCKOUT|ABT_MODE
msr cpsr_all, r1
ldr sp, =_ABT_STACK_ADDRESS
orr r1, r0, #LOCKOUT|UND_MODE
msr cpsr_all, r1
ldr sp, =_UND_STACK_ADDRESS
orr r1, r0, #LOCKOUT|SVC_MODE
msr cpsr_all, r1
ldr sp, =_SVC_STACK_ADDRESS
b Initialize_Data
.ltorg
Initialize_Data:
ldr r0, =Image_RO_Limit
ldr r1, =Image_RW_Base
ldr r2, =Image_ZI_Base
ldr r3, =Image_ZI_Limit
mov r4, #0x00
cmp r0, r1
beq data1
data0:
cmp r1, r2
ldrcc r5, [r0], #4
strcc r5, [r1], #4
bcc data0
data1:
cmp r2, r3
strcc r4, [r2], #4
bcc data1
b Initialize_Entry
.ltorg
.extern _os_entry
Initialize_Entry:
mov r0, #SYS_MODE
msr cpsr_all, r0
ldr sp, =_USR_STACK_ADDRESS
bl _os_entry
b .
.ltorg
.extern Isr_UndefineHandler
SystemUndefinedHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_UndefineHandler
ldmfd sp!, {r0-r3, ip, pc}^
.extern Isr_SwiHandler
SystemSwiHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
ldr r1, [r0]
bic r1, r1, #0xff000000
bl Isr_SwiHandler
ldmfd sp!, {r0-r3, ip, pc}^
.extern Isr_PrefetchAbortHandler
SystemPrefetchHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_PrefetchAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
.extern Isr_DataAbortHandler
SystemAbortHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #8
bl Isr_DataAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #8
.extern _irq_entry
SystemIrqHandler:
stmfd sp!, {r0-r3, ip, lr}
ldr r0, =INTOFFSET
ldr r0, [r0]
b _irq_entry
.ltorg
.extern _irq_entry
SystemFiqHandler:
stmfd sp!, {r0-r3, ip, lr}
ldr r1, =SRCPND
ldr r1, [r1]
cmp r1, #0x00
beq fiq2
mov r0, #0x00
fiq0:
movs r1, r1, lsr #1
bcs fiq1
add r0, r0, #1
b fiq0
fiq1:
b _irq_entry
fiq2:
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
.ltorg
.end
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