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📄 start_gcc.s

📁 一个基于ARM9的操作系统, 实现了很多的功能,包括内存管理,进程创建等
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/*
* file:
*       start.S
* description:
*       at91sam7s64 startup code.
*/

/* MEMORY AREA */
#define _RAM_STARTADDRESS   0x00200000
#define _RAM_ENDADDRESS     0x00204000
#define _ROM_STARTADDRESS   0x00000000
#define _ROM_ENDADDRESS     0x00010000


/* STACK DEFINITIONS */
#define _FIQ_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00000)   /* 896 */
#define _IRQ_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00000)   /* 896 */
#define _ABT_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00380)   /* 128 */
#define _SVC_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00380)   /* 128 */
#define _UND_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00380)   /* 128 */
#define _USR_STACK_ADDRESS  (_RAM_ENDADDRESS-0x00400)   /* 0K  */


/* PROCESSOR MODE */
#define FIQ_MODE    0x11        /* Fast Interrupt Mode (FIQ) */
#define IRQ_MODE    0x12        /* Interrupt Mode (IRQ)      */
#define ABT_MODE    0x17        /* Abort Mode(ABT)           */
#define SVC_MODE    0x13        /* Supervisor Mode (SVC)     */
#define UND_MODE    0x1b        /* Undefine Mode(UDF)        */
#define USR_MODE    0x10        /* User Mode(USR)            */
#define SYS_MODE    0x1f        /* System Mode(SYS)          */
#define MODE_MSK    0x1f        /* Processor Mode Mask       */


/* IRQ BITS */
#define F_BIT       0x40        /* FIQ Disable                  */
#define I_BIT       0x80        /* IRQ Disable                  */
#define LOCKOUT     0xc0        /* Interrupt lockout mask value */


/* RESET CONTROLLER USER INTERFACE */
#define RSTC_RCR    0xfffffd00
#define RSTC_RSR    0xfffffd04
#define RSTC_RMR    0xfffffd08


/* WATCHDOG TIMER USER INTERFACE */
#define WDTC_WDCR   0xfffffd40
#define WDTC_WDMR   0xfffffd44
#define WDTC_WDSR   0xfffffd48


/* ADVANCED INTERRUPT CONTROLLER USER INTERFACE */
#define AIC_IVR     0xfffff100
#define AIC_FVR     0xfffff104
#define AIC_ISR     0xfffff108
#define AIC_IPR     0xfffff10c
#define AIC_IMR     0xfffff110
#define AIC_CISR    0xfffff114
#define AIC_IECR    0xfffff120
#define AIC_IDCR    0xfffff124
#define AIC_ICCR    0xfffff128
#define AIC_ISCR    0xfffff12c
#define AIC_EOICR   0xfffff130
#define AIC_SPU     0xfffff134
#define AIC_DCR     0xfffff138
#define AIC_FFER    0xfffff140
#define AIC_FFDR    0xfffff144
#define AIC_FFSR    0xfffff148


/* EMBEDDED FLASH CONTROLLER USER INTERFACE */
#define MC_FMR      0xffffff60
#define MC_FCR      0xffffff64
#define MC_FSR      0xffffff68


/* POWER MANAGEMENT USER INTERFACE */
#define PMC_SCER    0xfffffc00
#define PMC_SCDR    0xfffffc04
#define PMC_SCSR    0xfffffc08
#define PMC_PCER    0xfffffc10
#define PMC_PCDR    0xfffffc14
#define PMC_PCSR    0xfffffc18
#define PMC_MOR     0xfffffc20
#define PMC_MCFR    0xfffffc24
#define PMC_PLLR    0xfffffc2c
#define PMC_MCKR    0xfffffc30
#define PMC_ACKR    0xfffffc34
#define PMC_PCK0    0xfffffc40
#define PMC_PCK1    0xfffffc44
#define PMC_PCK2    0xfffffc48
#define PMC_PCK3    0xfffffc4c
#define PMC_IER     0xfffffc60
#define PMC_IDR     0xfffffc64
#define PMC_SR      0xfffffc68
#define PMC_IMR     0xfffffc6c


/* STARTUP CODE */
.text
        .global _start
_start:
        b       SystemResetHandler
        b       SystemUndefinedHandler
        b       SystemSwiHandler
        b       SystemPrefetchHandler
        b       SystemAbortHandler
        b       SystemReservedHandler
        b       SystemIrqHandler
        b       SystemFiqHandler
        .ltorg


SystemReservedHandler:
        b       SystemReservedHandler


SystemResetHandler:
        ldr     r0, =RSTC_RMR
        ldr     r1, =0x5a000001
        str     r1,[r0]

        ldr     r0, =WDTC_WDMR
        ldr     r1, =0x8000
        str     r1,[r0]

        ldr     r0, =AIC_IDCR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_FFDR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_ICCR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_EOICR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        b       Initialize_Memory
        .ltorg


Initialize_Memory:
        ldr     r0, =MC_FMR
        ldr     r1, =0x00320100
        str     r1, [r0]

        b       Initialize_Clock
        .ltorg


Initialize_Clock:
        ldr     r0, =PMC_MOR
        ldr     r1, =0x0601
        str     r1, [r0]
wait0:
        ldr     r0, =PMC_SR
        ldr     r1, [r0]
        mov     r1, r1, lsl #31
        mov     r1, r1, lsr #31
        cmp     r1, #0x01
        bne     wait0

        ldr     r0, =PMC_PLLR       /* Fout = (18.432/5)*(25+1) = 95.846400 Mhz */
        ldr     r1, =0x00191c05
        str     r1, [r0]
wait1:
        ldr     r0, =PMC_SR
        ldr     r1, [r0]
        mov     r1, r1, lsl #29
        mov     r1, r1, lsr #31
        cmp     r1, #0x01
        bne     wait1

        ldr     r0, =PMC_MCKR       /* MCK = PLL Fout / 2 = 47.923200 Mhz */
        ldr     r1, =0x07
        str     r1, [r0]

        b       Initialize_Stack
        .ltorg


Initialize_Stack:
        mov     r0, #0x00

        orr     r1, r0, #LOCKOUT|FIQ_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_FIQ_STACK_ADDRESS

        orr     r1, r0, #I_BIT|IRQ_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_IRQ_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|ABT_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_ABT_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|UND_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_UND_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|SVC_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_SVC_STACK_ADDRESS

        b       Initialize_Data
        .ltorg


        .extern Image_RO_Base
        .extern Image_RO_Limit
        .extern Image_RW_Base
        .extern Image_RW_Limit
        .extern Image_ZI_Base
        .extern Image_ZI_Limit
Initialize_Data:
        ldr     r0, =Image_RO_Limit
        ldr     r1, =Image_RW_Base
        ldr     r2, =Image_ZI_Base
        ldr     r3, =Image_ZI_Limit
        mov     r4, #0x00

        cmp     r0, r1
        beq     data1
data0:
        cmp     r1, r2
        ldrcc   r5, [r0], #4
        strcc   r5, [r1], #4
        bcc     data0
data1:
        cmp     r2, r3
        strcc   r4, [r2], #4
        bcc     data1

        b       Initialize_Entry
        .ltorg


        .extern _os_entry
Initialize_Entry:
        mov     r0, #SYS_MODE
        msr     cpsr_cxsf, r0
        ldr     sp, =_USR_STACK_ADDRESS

        bl      _os_entry
        b       .
        .ltorg


        .extern Isr_UndefineHandler
SystemUndefinedHandler:
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        bl      Isr_UndefineHandler
        ldmfd   sp!, {r0-r3, ip, pc}^


        .extern Isr_SwiHandler
SystemSwiHandler:
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        ldr     r1, [r0]
        bic     r1, r1, #0xff000000
        bl      Isr_SwiHandler
        ldmfd   sp!, {r0-r3, ip, pc}^


        .extern Isr_PrefetchAbortHandler
SystemPrefetchHandler:
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        bl      Isr_PrefetchAbortHandler
        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4


        .extern Isr_DataAbortHandler
SystemAbortHandler:
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #8
        bl      Isr_DataAbortHandler
        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #8


        .extern _irq_entry
SystemIrqHandler:
        stmfd   sp!, {r0-r3, ip, lr}

        ldr     r2, =AIC_IVR
        ldr     r2, [r2]

        ldr     r1, =AIC_ISR
        ldr     r1, [r1]
        and     r0, r1, #0x1f

        cmp     r2, #0x00
        bne     _irq_entry

        ldr     r1, =AIC_EOICR
        ldr     r0, [r1]
        str     r0, [r1]

        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4
        .ltorg


        .extern _irq_entry
SystemFiqHandler:
        stmfd   sp!, {r0-r3, ip, lr}

        ldr     r2, =AIC_FVR
        ldr     r2, [r2]

        ldr     r1, =AIC_IPR
        ldr     r1, [r1]
        mov     r1, r1, lsr #1
        cmp     r1, #0x00
        beq     fiq2
        mov     r0, #0x01
fiq0:
        movs    r1, r1, lsr #1
        bcs     fiq1
        add     r0, r0, #1
        b       fiq0
fiq1:
        cmp     r2, #0x00
        bne     _irq_entry
fiq2:
        ldr     r1, =AIC_EOICR
        ldr     r0, [r1]
        str     r0, [r1]

        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4
        .ltorg


        .end

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