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📄 start.s

📁 一个基于ARM9的操作系统, 实现了很多的功能,包括内存管理,进程创建等
💻 S
字号:
;
; file:
;       start.S
; description:
;       at91sam7s64 startup code.
;

; MEMORY AREA
_RAM_STARTADDRESS   EQU 0x00200000
_RAM_ENDADDRESS     EQU 0x00204000
_ROM_STARTADDRESS   EQU 0x00000000
_ROM_ENDADDRESS     EQU 0x00010000


; STACK DEFINITIONS
_FIQ_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00000)   ; 896
_IRQ_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00000)   ; 896
_ABT_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00380)   ; 128
_SVC_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00380)   ; 128
_UND_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00380)   ; 128
_USR_STACK_ADDRESS  EQU (_RAM_ENDADDRESS-0x00400)   ; 0K


; PROCESSOR MODE
FIQ_MODE    EQU     0x11        ; Fast Interrupt Mode (FIQ)
IRQ_MODE    EQU     0x12        ; Interrupt Mode (IRQ)
ABT_MODE    EQU     0x17        ; Abort Mode(ABT)
SVC_MODE    EQU     0x13        ; Supervisor Mode (SVC)
UND_MODE    EQU     0x1b        ; Undefine Mode(UDF)
USR_MODE    EQU     0x10        ; User Mode(USR)
SYS_MODE    EQU     0x1f        ; System Mode(SYS)
MODE_MSK    EQU     0x1f        ; Processor Mode Mask


; IRQ BITS
F_BIT       EQU     0x40        ; FIQ Disable
I_BIT       EQU     0x80        ; IRQ Disable
LOCKOUT     EQU     0xc0        ; Interrupt lockout mask value


; RESET CONTROLLER USER INTERFACE
RSTC_RCR    EQU     0xfffffd00
RSTC_RSR    EQU     0xfffffd04
RSTC_RMR    EQU     0xfffffd08


; WATCHDOG TIMER USER INTERFACE
WDTC_WDCR   EQU     0xfffffd40
WDTC_WDMR   EQU     0xfffffd44
WDTC_WDSR   EQU     0xfffffd48


; ADVANCED INTERRUPT CONTROLLER USER INTERFACE
AIC_IVR     EQU     0xfffff100
AIC_FVR     EQU     0xfffff104
AIC_ISR     EQU     0xfffff108
AIC_IPR     EQU     0xfffff10c
AIC_IMR     EQU     0xfffff110
AIC_CISR    EQU     0xfffff114
AIC_IECR    EQU     0xfffff120
AIC_IDCR    EQU     0xfffff124
AIC_ICCR    EQU     0xfffff128
AIC_ISCR    EQU     0xfffff12c
AIC_EOICR   EQU     0xfffff130
AIC_SPU     EQU     0xfffff134
AIC_DCR     EQU     0xfffff138
AIC_FFER    EQU     0xfffff140
AIC_FFDR    EQU     0xfffff144
AIC_FFSR    EQU     0xfffff148


; EMBEDDED FLASH CONTROLLER USER INTERFACE
MC_FMR      EQU     0xffffff60
MC_FCR      EQU     0xffffff64
MC_FSR      EQU     0xffffff68


; POWER MANAGEMENT USER INTERFACE
PMC_SCER    EQU     0xfffffc00
PMC_SCDR    EQU     0xfffffc04
PMC_SCSR    EQU     0xfffffc08
PMC_PCER    EQU     0xfffffc10
PMC_PCDR    EQU     0xfffffc14
PMC_PCSR    EQU     0xfffffc18
PMC_MOR     EQU     0xfffffc20
PMC_MCFR    EQU     0xfffffc24
PMC_PLLR    EQU     0xfffffc2c
PMC_MCKR    EQU     0xfffffc30
PMC_ACKR    EQU     0xfffffc34
PMC_PCK0    EQU     0xfffffc40
PMC_PCK1    EQU     0xfffffc44
PMC_PCK2    EQU     0xfffffc48
PMC_PCK3    EQU     0xfffffc4c
PMC_IER     EQU     0xfffffc60
PMC_IDR     EQU     0xfffffc64
PMC_SR      EQU     0xfffffc68
PMC_IMR     EQU     0xfffffc6c


; STARTUP CODE
        AREA    start, CODE, READONLY, ALIGN=4
        CODE32

        ENTRY
        b       SystemResetHandler
        b       SystemUndefinedHandler
        b       SystemSwiHandler
        b       SystemPrefetchHandler
        b       SystemAbortHandler
        b       SystemReservedHandler
        b       SystemIrqHandler
        b       SystemFiqHandler
        LTORG


SystemReservedHandler
        b       SystemReservedHandler


SystemResetHandler
        ldr     r0, =RSTC_RMR
        ldr     r1, =0x5a000001
        str     r1,[r0]

        ldr     r0, =WDTC_WDMR
        ldr     r1, =0x8000
        str     r1,[r0]

        ldr     r0, =AIC_IDCR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_FFDR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_ICCR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        ldr     r0, =AIC_EOICR
        ldr     r1, =0xffffffff
        str     r1, [r0]

        b       Initialize_Memory
        LTORG


Initialize_Memory
        ldr     r0, =MC_FMR
        ldr     r1, =0x00320100
        str     r1, [r0]

        b       Initialize_Clock
        LTORG


Initialize_Clock
        ldr     r0, =PMC_MOR
        ldr     r1, =0x0601
        str     r1, [r0]
0
        ldr     r0, =PMC_SR
        ldr     r1, [r0]
        mov     r1, r1, lsl #31
        mov     r1, r1, lsr #31
        cmp     r1, #0x01
        bne     %B0

        ldr     r0, =PMC_PLLR       ; Fout = (18.432/5)*(25+1) = 95.846400 Mhz
        ldr     r1, =0x00191c05
        str     r1, [r0]
1
        ldr     r0, =PMC_SR
        ldr     r1, [r0]
        mov     r1, r1, lsl #29
        mov     r1, r1, lsr #31
        cmp     r1, #0x01
        bne     %B1

        ldr     r0, =PMC_MCKR       ; MCK = PLL Fout / 2 = 47.923200 Mhz
        ldr     r1, =0x07
        str     r1, [r0]

        b       Initialize_Stack
        LTORG


Initialize_Stack
        mov     r0, #0x00

        orr     r1, r0, #LOCKOUT|FIQ_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_FIQ_STACK_ADDRESS

        orr     r1, r0, #I_BIT|IRQ_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_IRQ_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|ABT_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_ABT_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|UND_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_UND_STACK_ADDRESS

        orr     r1, r0, #LOCKOUT|SVC_MODE
        msr     cpsr_cxsf, r1
        ldr     sp, =_SVC_STACK_ADDRESS

        b       Initialize_Data
        LTORG


        IMPORT  |Image$$RO$$Base|
        IMPORT  |Image$$RO$$Limit|
        IMPORT  |Image$$RW$$Base|
        IMPORT  |Image$$RW$$Limit|
        IMPORT  |Image$$ZI$$Base|
        IMPORT  |Image$$ZI$$Limit|
Initialize_Data
        ldr     r0, =|Image$$RO$$Limit|
        ldr     r1, =|Image$$RW$$Base|
        ldr     r2, =|Image$$ZI$$Base|
        ldr     r3, =|Image$$ZI$$Limit|
        mov     r4, #0x00

        cmp     r0, r1
        beq     %F1
0
        cmp     r1, r2
        ldrcc   r5, [r0], #4
        strcc   r5, [r1], #4
        bcc     %B0
1
        cmp     r2, r3
        strcc   r4, [r2], #4
        bcc     %B1

        b       Initialize_Entry
        LTORG


        IMPORT  _os_entry
Initialize_Entry
        mov     r0, #SYS_MODE
        msr     cpsr_cxsf, r0
        ldr     sp, =_USR_STACK_ADDRESS

        bl      _os_entry
        b       .
        LTORG


        IMPORT  Isr_UndefineHandler
SystemUndefinedHandler
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        bl      Isr_UndefineHandler
        ldmfd   sp!, {r0-r3, ip, pc}^


        IMPORT  Isr_SwiHandler
SystemSwiHandler
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        ldr     r1, [r0]
        bic     r1, r1, #0xff000000
        bl      Isr_SwiHandler
        ldmfd   sp!, {r0-r3, ip, pc}^


        IMPORT  Isr_PrefetchAbortHandler
SystemPrefetchHandler
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #4
        bl      Isr_PrefetchAbortHandler
        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4


        IMPORT  Isr_DataAbortHandler
SystemAbortHandler
        stmfd   sp!, {r0-r3, ip, lr}
        sub     r0, lr, #8
        bl      Isr_DataAbortHandler
        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #8


        IMPORT  _irq_entry
SystemIrqHandler
        stmfd   sp!, {r0-r3, ip, lr}

        ldr     r2, =AIC_IVR
        ldr     r2, [r2]

        ldr     r1, =AIC_ISR
        ldr     r1, [r1]
        and     r0, r1, #0x1f

        cmp     r2, #0x00
        bne     _irq_entry

        ldr     r1, =AIC_EOICR
        ldr     r0, [r1]
        str     r0, [r1]

        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4
        LTORG


        IMPORT  _irq_entry
SystemFiqHandler
        stmfd   sp!, {r0-r3, ip, lr}

        ldr     r2, =AIC_FVR
        ldr     r2, [r2]

        ldr     r1, =AIC_IPR
        ldr     r1, [r1]
        mov     r1, r1, lsr #1
        cmp     r1, #0x00
        beq     %F2
        mov     r0, #0x01
0
        movs    r1, r1, lsr #1
        bcs     %F1
        add     r0, r0, #1
        b       %B0
1
        cmp     r2, #0x00
        bne     _irq_entry
2
        ldr     r1, =AIC_EOICR
        ldr     r0, [r1]
        str     r0, [r1]

        ldmfd   sp!, {r0-r3, ip, lr}
        subs    pc, lr, #4
        LTORG


        END

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