📄 aci3_2.asm
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; verifying the ISR
LACC isr_ticker
ADD #1
SACL isr_ticker
;---------------------------------------------------------
;SYSTEM PHASE INCREMENTAL BUILD OPTIONS - Main code
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase1_inc_build)
;---------------------------------------------------------
LDP #vhz_freq
BLDD #freq_testing,vhz_freq
CALL V_Hz_PROFILE
CALL DAC_VIEW_DRV
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase2_inc_build)
;---------------------------------------------------------
LDP #target_value
BLDD #freq_testing,target_value
CALL RAMP_CNTL
LDP #vhz_freq
BLDD #setpt_value,vhz_freq
CALL V_Hz_PROFILE
LDP #sv_freq
BLDD #vhz_freq,sv_freq
BLDD #v_out,sv_gain
CALL SVGEN_MF
LDP #Mfunc_c1
BLDD #Ta,Mfunc_c1
BLDD #Tb,Mfunc_c2
BLDD #Tc,Mfunc_c3
CALL FC_PWM_DRV
CALL DAC_VIEW_DRV
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase3_inc_build)
;---------------------------------------------------------
POINT_B0
LDP #target_value
BLDD #freq_testing,target_value
CALL RAMP_CNTL
LDP #vhz_freq
BLDD #setpt_value,vhz_freq
CALL V_Hz_PROFILE
LDP #sv_freq
BLDD #vhz_freq,sv_freq
BLDD #v_out,sv_gain
CALL SVGEN_MF
LDP #Mfunc_c1
BLDD #Ta,Mfunc_c1
BLDD #Tb,Mfunc_c2
BLDD #Tc,Mfunc_c3
CALL FC_PWM_DRV
CALL ILEG2_DCBUS_DRV
LDP #DC_bus
BLDD #Vdc_meas,DC_bus
BLDD #Ta,Mfunc_V1
BLDD #Tb,Mfunc_V2
BLDD #Tc,Mfunc_V3
CALL PHASE_VOLTAGE_CALC
CALL DAC_VIEW_DRV
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase4_inc_build)
;---------------------------------------------------------
POINT_B0
LDP #target_value
BLDD #freq_testing,target_value
CALL RAMP_CNTL
LDP #vhz_freq
BLDD #setpt_value,vhz_freq
CALL V_Hz_PROFILE
LDP #sv_freq
BLDD #vhz_freq,sv_freq
BLDD #v_out,sv_gain
CALL SVGEN_MF
LDP #Mfunc_c1
BLDD #Ta,Mfunc_c1
BLDD #Tb,Mfunc_c2
BLDD #Tc,Mfunc_c3
CALL FC_PWM_DRV
;Check for Capture event from Hall sensor (sprocket)
POINT_EV
BIT IFRC, BIT0 ;Check CAP flag for edge transition on CAP1 pin
BCND SKIP_SPEED, NTC ;If no edge present skip speed routine
CALL CAP_EVENT_DRV
LACC FIFO1 ;Else fetch "Time-stamp" & proceed with Speed meas.
LDP #time_stamp
SACL time_stamp
CALL SPEED_PRD
POINT_EV
SPLK #0FFFFh,IFRC ;Clear all CAP flags
SKIP_SPEED
CALL ILEG2_DCBUS_DRV
LDP #clark_a
BLDD #Imeas_a,clark_a
BLDD #Imeas_b,clark_b
CALL CLARKE
LDP #DC_bus
BLDD #Vdc_meas,DC_bus
BLDD #Ta,Mfunc_V1
BLDD #Tb,Mfunc_V2
BLDD #Tc,Mfunc_V3
CALL PHASE_VOLTAGE_CALC
LDP #ualfa_mras
BLDD #Vdirect,ualfa_mras
BLDD #Vquadra,ubeta_mras
BLDD #clark_d,ialfa_mras
BLDD #clark_q,ibeta_mras
CALL ACI_MRAS
LDP #BC_IN
BLDD #wr_hat_mras,BC_IN
CALL BC_CALC
CALL DAC_VIEW_DRV
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase5_inc_build)
;---------------------------------------------------------
POINT_B0
; checking the close-loop flag here
LACC cl_flag ; ready to be close-loop ?
BCND CLOSE_LOOP,GT ; Branch for the close-loop system
OPEN_LOOP
SPLK #7EB8h,GPR0 ; It is 0.99, assuming slip is 1%
LT freq_testing
MPY GPR0
PAC
SACH speed_ref,1
LDP #pid_ref_reg1
BLDD #speed_ref,pid_ref_reg1
; BLDD #wr_hat_mras,pid_fb_reg1 ; for sensorless
BLDD #BC_OUT,pid_fb_reg1 ; for sensorless (averaged)
CALL PID_REG1
LDP #pid_out_reg1
LACC pid_out_reg1 ; pid_out_reg1 is compensating slip
ADD pid_ref_reg1 ; add reference speed here
POINT_B0
SACL syn_speed ; here is syn. speed
LDP #target_value
BLDD #freq_testing,target_value
CALL RAMP_CNTL
LDP #vhz_freq
BLDD #setpt_value,vhz_freq
B SKIP_CL
CLOSE_LOOP
LDP #target_value
BLDD #speed_ref,target_value
CALL RAMP_CNTL
LDP #pid_ref_reg1
BLDD #setpt_value,pid_ref_reg1
; BLDD #wr_hat_mras,pid_fb_reg1 ; for sensorless
BLDD #BC_OUT,pid_fb_reg1 ; for sensorless (averaged)
; BLDD #speed_prd,pid_fb_reg1 ; for sensor
CALL PID_REG1
LDP #pid_out_reg1
LACC pid_out_reg1 ; pid_out_reg1 is compensating slip
ADD pid_ref_reg1 ; add reference speed here
POINT_B0
SACL syn_speed ; here is syn. speed
SACL freq_testing ; update freq_testing for smoothly returning open-loop
LDP #vhz_freq
BLDD #syn_speed,vhz_freq
POINT_B0
SKIP_CL
CALL V_Hz_PROFILE
LDP #sv_freq
BLDD #vhz_freq,sv_freq
BLDD #v_out,sv_gain
CALL SVGEN_MF
LDP #Mfunc_c1
BLDD #Ta,Mfunc_c1
BLDD #Tb,Mfunc_c2
BLDD #Tc,Mfunc_c3
CALL FC_PWM_DRV
;Check for Capture event from Hall sensor (sprocket)
POINT_EV
BIT IFRC, BIT0 ;Check CAP flag for edge transition on CAP1 pin
BCND SKIP_SPEED, NTC ;If no edge present skip speed routine
CALL CAP_EVENT_DRV
LACC FIFO1 ;Else fetch "Time-stamp" & proceed with Speed meas.
LDP #time_stamp
SACL time_stamp
CALL SPEED_PRD
POINT_EV
SPLK #0FFFFh,IFRC ;Clear all CAP flags
SKIP_SPEED
CALL ILEG2_DCBUS_DRV
LDP #clark_a
BLDD #Imeas_a,clark_a
BLDD #Imeas_b,clark_b
CALL CLARKE
LDP #DC_bus
BLDD #Vdc_meas,DC_bus
BLDD #Ta,Mfunc_V1
BLDD #Tb,Mfunc_V2
BLDD #Tc,Mfunc_V3
CALL PHASE_VOLTAGE_CALC
LDP #ualfa_mras
BLDD #Vdirect,ualfa_mras
BLDD #Vquadra,ubeta_mras
BLDD #clark_d,ialfa_mras
BLDD #clark_q,ibeta_mras
CALL ACI_MRAS
LDP #BC_IN
BLDD #wr_hat_mras,BC_IN
CALL BC_CALC
CALL DAC_VIEW_DRV
.endif
;---------------------------------------------------------
; Change synchronous speed from pu value to rpm value (Q15 -> Q0)
POINT_B0
SPLK #28800, GPR1 ; GPR1 = base speed (3600 rpm) (Q3)
LT GPR1 ; TREG = GPR1 (Q3)
MPY freq_testing ; PREG = GPR1*freq_testing (Q18)
PAC ; ACC = GPR1*freq_testing (Q18)
SFR ; ACC = GPR1*freq_testing (Q17)
SFR ; ACC = GPR1*freq_testing (Q16)
SACH freq_testing_rpm ; freq_testing_rmp = GPR1*freq_testing (Q0)
; Change reference speed from pu value to rpm value (Q15 -> Q0)
MPY speed_ref ; PREG = GPR1*speed_ref (Q18)
PAC ; ACC = GPR1*speed_ref (Q18)
SFR ; ACC = GPR1*speed_ref (Q17)
SFR ; ACC = GPR1*speed_ref (Q16)
SACH speed_ref_rpm ; speed_ref_rpm = GPR1*speed_ref (Q0)
;=========================================================
;End main section of ISR
;=========================================================
;Context restore regs
END_ISR:
POINT_PG0
MAR *, AR1 ; make stack pointer active
MAR *- ; point to top of stack
;More context restore if needed
PSHD *- ; restore TOS
LAR AR6,*- ; restore AR6
LACL *- ; Restore Acc low
ADD *-,16 ; Restore Acc high
LST #0, *- ; Restore ST0
LST #1, *- ; Restore ST1 and pointer
EINT
RET
;==============================================================================
; I S R - PHANTOM
;
; Description: Dummy ISR, used to trap spurious interrupts.
;
; Modifies:
;
; Last Update: 16-06-95
;==============================================================================
PHANTOM B PHANTOM
PHANTOM1 B PHANTOM1
PHANTOM2 B PHANTOM2
PHANTOM3 B PHANTOM3
PHANTOM4 B PHANTOM4
PHANTOM5 B PHANTOM5
PHANTOM6 B PHANTOM6⌨️ 快捷键说明
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