📄 aci3_2.asm
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;==============================================================================
; System Name: ACI3_2
;
; File Name: ACI3_2.ASM
;
; Description: Sensorless control of Induction Motor by Volts/Hertz technique
; using MRAS speed estimator
;
; Originator: Digital control systems Group - Texas Instruments
;
; Target dependency: x243/x2407
; For x243 use 15kHz sampling frequency
; To Select the target device see x24x_app.h file.
;
;
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
;==============================================================================
;******************************************************************************
; SYSTEM OPTIONS
;******************************************************************************
real_time .set 1 ; 1 for real time mode, otherwise set 0
;******************************************************************************
;-----------------------------------------------------------------------------
phase1_inc_build .set 1 ; V/Hz profile test
phase2_inc_build .set 0 ; SV_GEN and FC_PWM tests
phase3_inc_build .set 0 ; Currents and DC-bus volt measurement tests
phase4_inc_build .set 0 ; Speed measurement and MRAS speed estimator tests
phase5_inc_build .set 0 ; Sensorless closed-loop V/Hz system test
;-----------------------------------------------------------------------------
; External references
;-----------------------------------------------------------------------------
.include "x24x_app.h"
.global MON_RT_CNFG
.ref SYS_INIT
.ref CAP_EVENT_DRV, CAP_EVENT_DRV_INIT ;function call
.ref CAP_EVENT_DRV_CLKPS_INIT ;function call
.ref CLK_prescaler_bits ;Parameter
.ref SPEED_PRD, SPEED_PRD_INIT ;function call
.ref time_stamp ;Input
.ref rpm_max, speed_scaler,shift ;parameter
.ref speed_prd, speed_rpm ;Outputs
.ref DAC_VIEW_DRV,DAC_VIEW_DRV_INIT ; function call
.ref DAC_IPTR0,DAC_IPTR1,DAC_IPTR2,DAC_IPTR3 ; Inputs
.ref RAMP_CNTL, RAMP_CNTL_INIT ; function call
.ref target_value ; Inputs
.ref rmp_dly_max, rmp_lo_limit ; Input Parameters
.ref rmp_hi_limit ; Input Parameter
.ref setpt_value, s_eq_t_flg ; Outputs
.ref V_Hz_PROFILE, V_Hz_PROFILE_INIT ;function call
.ref vhz_freq ;Inputs
.ref v_out ;Outputs
.ref SVGEN_MF, SVGEN_MF_INIT ;function call
.ref sv_gain, sv_offset, sv_freq ;Inputs
.ref Ta, Tb, Tc ;Outputs
.ref FC_PWM_DRV, FC_PWM_DRV_INIT ;function call
.ref Mfunc_c1, Mfunc_c2, Mfunc_c3, Mfunc_p ;Inputs
.ref CLARKE, CLARKE_INIT ;function call
.ref clark_a, clark_b ;Inputs
.ref clark_d, clark_q ;Outputs
.ref ILEG2_DCBUS_DRV, ILEG2_DCBUS_DRV_INIT ;function call
.ref Ch_sel, Imeas_a_gain, Imeas_b_gain, Vdc_meas_gain ;Inputs
.ref Imeas_a_offset, Imeas_b_offset, Vdc_meas_offset ;Inputs
.ref Imeas_a,Imeas_b,Imeas_c ;Outputs
.ref Vdc_meas ;Outputs
.ref PHASE_VOLTAGE_CALC ;function call
.ref PHASE_VOLTAGE_CALC_INIT ;function call
.ref Mfunc_V1, Mfunc_V2 ;Inputs
.ref Mfunc_V3, DC_bus ;Inputs
.ref Vphase_A,Vphase_B,Vphase_C ;Outputs
.ref Vdirect,Vquadra ;Outputs
.ref ACI_MRAS, ACI_MRAS_INIT ;function call
.ref ualfa_mras, ubeta_mras ;Inputs
.ref ialfa_mras, ibeta_mras ;Inputs
.ref wr_hat_mras, wr_hat_rpm_mras ;Outputs
.ref PID_REG1, PID_REG1_INIT ;function call
.ref pid_fb_reg1, pid_ref_reg1 ;Inputs
.ref pid_out_reg1 ;Output
.ref BC_INIT,BC_CALC ;function call
.ref BC_IN,BC_OUT ;Inputs/Outputs
;-----------------------------------------------------------------------------
; Local Variable Declarations
;-----------------------------------------------------------------------------
.def GPR0 ;General purpose registers.
.def GPR1
.def GPR2
.def GPR3
.def GPR4
.def COMCON
.bss GPR0,1 ;General purpose registers.
.bss GPR1,1
.bss GPR2,1
.bss GPR3,1
.bss GPR4,1
.bss freq_testing,1
.bss freq_testing_rpm,1
.bss speed_ref,1
.bss speed_ref_rpm,1
.bss syn_speed,1
.bss cl_flag,1
.bss isr_ticker,1
;==============================================================================
; V E C T O R T A B L E ( including RT monitor traps )
;==============================================================================
.include "c200mnrt.i" ; Include conditional assembly options.
.sect "vectors"
.def _c_int0
RESET B _c_int0 ; 00
INT1 B PHANTOM ; 02
INT2 B T1UF_ISR ; 04
INT3 B PHANTOM ; 06
INT4 B PHANTOM ; 08
INT5 B PHANTOM ; 0A
INT6 B PHANTOM ; 0C
.include "rtvecs.h"
; Note : The above include line must be AFTER the user configurable
; vectors. Do not change the place where this line is included.
;==============================================================================
; M A I N C O D E - starts here
;==============================================================================
.text
_c_int0:
CALL SYS_INIT
CALL DAC_VIEW_DRV_INIT
CALL RAMP_CNTL_INIT
CALL V_Hz_PROFILE_INIT
CALL SVGEN_MF_INIT
CALL FC_PWM_DRV_INIT
CALL SPEED_PRD_INIT
CALL CAP_EVENT_DRV_INIT
CALL ILEG2_DCBUS_DRV_INIT
CALL PHASE_VOLTAGE_CALC_INIT
CALL CLARKE_INIT
CALL ACI_MRAS_INIT
CALL PID_REG1_INIT
CALL BC_INIT
;------------------------------------------------------------------------------------------
;System time-base init
;------------------------------------------------------------------------------------------
; Here time base is derived from T1 Underflow Int (i.e. Period)
; in FC_PWM_DRV_INIT module (see PWM_DRV.ASM).
;----------------------------------------------------------
; Initialise the Real time monitor
;----------------------------------------------------------
;---Real Time option---------------
.if (real_time)
CALL MON_RT_CNFG ;For Real-Time
.endif
;----------------------------------
;----------------------------------------------------------
; System Interrupt Init.
;----------------------------------------------------------
;Event Manager
POINT_EV
; SPLK #0000001000000000b,IMRA ;Enable T1 Underflow Int (i.e. Period)
SPLK #0000001000000001b,IMRA ;Enable T1 Underflow Int (i.e. Period)
; SPLK #0000000000000100b,IMRB ;Enable T2 Underflow Int (i.e. Period)
; SPLK #0000000000000100b,IMRC ;Enable CAP3 int (i.e. QEP index pulse)
;||||!!!!||||!!!!
;5432109876543210
SPLK #0FFFFh,IFRA ; Clear all Group A interrupt flags
SPLK #0FFFFh,IFRB ; Clear all Group B interrupt flags
SPLK #0FFFFh,IFRC ; Clear all Group C interrupt flags
;C2xx Core
POINT_PG0
;---Real Time option --------------------------------------------------
.if (real_time)
SPLK #0000000001000010b,IMR ;En Int lvl 2,7 (T1 ISR)
; SPLK #0000000001000100b,IMR ;En Int lvl 3,7 (T2 ISR)
;5432109876543210
.endif
.if (real_time != 1)
SPLK #0000000000000010b,IMR ;En Int lvl 2 (T1 ISR)
; SPLK #0000000000000100b,IMR ;En Int lvl 3 (T2 ISR)
;||||!!!!||||!!!!
;5432109876543210
.endif
SPLK #0FFFFh, IFR ;Clear any pending Ints
EINT ;Enable global Ints
;-----------------------------------------------------------------------
;Enables PWM signals on DMC1500
;-----------------------------------------------------------------------
.if (x243|x2407) ;target dependancy
POINT_PF2
LACC OCRA
AND #0BFFFh
SACL OCRA ;Select Secondary function IOPB6
LACC PBDATDIR
OR #04000h
SACL PBDATDIR ;Set IOPB6 as output
LACC PBDATDIR
AND #0FFBFh ;Set IOPB6 low, Enable PWM
; OR #00040h ;Set IOPB6 high, Disable PWM
SACL PBDATDIR
.endif
;---------------------------------------------------------
;SYSTEM PHASE INCREMENTAL BUILD OPTIONS - Initialization
;---------------------------------------------------------
POINT_B0
;---------------------------------------------------------
.if (phase1_inc_build)
SPLK #03333h, freq_testing ; 40% of 120 Hz (48 Hz)
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase2_inc_build)
SPLK #03333h, freq_testing ; 40% of 120 Hz (48 Hz)
LDP #rmp_dly_max ; for Ramp control
SPLK #40,rmp_dly_max
LDP #DAC_IPTR0
SPLK #Ta,DAC_IPTR0
SPLK #Tb,DAC_IPTR1
SPLK #Tc,DAC_IPTR2
SPLK #v_out,DAC_IPTR3
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase3_inc_build)
SPLK #03333h, freq_testing ; 40% of 120 Hz (48 Hz)
LDP #rmp_dly_max ; for Ramp control
SPLK #40,rmp_dly_max
LDP #DAC_IPTR0
SPLK #Imeas_a,DAC_IPTR0
SPLK #Imeas_b,DAC_IPTR1
SPLK #Imeas_c,DAC_IPTR2
SPLK #Vdc_meas,DAC_IPTR3
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase4_inc_build)
SPLK #03333h, freq_testing ; 40% of 120 Hz (48 Hz)
LDP #rmp_dly_max ; for Ramp control
SPLK #40,rmp_dly_max
LDP #CLK_prescaler_bits ; for Capture driver
SPLK #7,CLK_prescaler_bits
CALL CAP_EVENT_DRV_CLKPS_INIT
LDP #DAC_IPTR0
SPLK #clark_d,DAC_IPTR0
SPLK #clark_q,DAC_IPTR1
SPLK #Vdirect,DAC_IPTR2
SPLK #Vquadra,DAC_IPTR3
.endif
;---------------------------------------------------------
;---------------------------------------------------------
.if (phase5_inc_build)
SPLK #03333h, freq_testing ; 40% of 120 Hz (48 Hz)
SPLK #031ECh, speed_ref ; 39% of 120 Hz (46.8 Hz)
SPLK #0h, cl_flag
LDP #rmp_dly_max ; for Ramp control
SPLK #40,rmp_dly_max
LDP #CLK_prescaler_bits ; for Capture driver
SPLK #7,CLK_prescaler_bits
CALL CAP_EVENT_DRV_CLKPS_INIT
LDP #DAC_IPTR0
SPLK #ialfa_mras,DAC_IPTR0
SPLK #ibeta_mras,DAC_IPTR1
SPLK #ualfa_mras,DAC_IPTR2
SPLK #ubeta_mras,DAC_IPTR3
.endif
;---------------------------------------------------------
;======================================================
MAIN: ;Main system background loop
;======================================================
M_1
B MAIN
;======================================================
;===========================================================================
; Routine Name: T1UF_ISR Routine Type: ISR
;
; Description:
;
;
; Originator: Digital control systems Group - Texas Instruments
;
; History:
;
;
; Last Update: 13-Jan 00
;===========================================================================
T1UF_ISR:
;Context save regs
MAR *,AR1 ; Save context
MAR *+ ; point to a guaranteed unused location
SST #1, *+ ; save ST1
SST #0, *+ ; save ST0
SACH *+ ; save acc high
SACL *+ ; save acc low
SAR AR6,*+ ; save AR6 (used by DAC)
POPD *+ ; save TOS to free h/w stack
;More context save if needed
POINT_EV
SPLK #0FFFFh,IFRA ; Clear all Group A interrupt flags (T1 ISR)
;=========================================================
;Start main section of ISR
;=========================================================
POINT_B0
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