dac_view.asm

无速度pid的异步电机vf控制的dsp调试程序

;===========================================================================
; File Name:	DAC_VIEW.asm
;
; Module Name:	DAC_VIEW_DRV	
;
; Initialization Routine: DAC_VIEW_DRV_INIT
;
; Originator:	Digital Control Systems Group
;			Texas Instruments
;
; Description:	Converts any s/w variable with Q15 representation into its 
;		equivalent Q0 format that spans the full input range of
;		a 12-bit DAC. Thus, it can be used to view the signal, 
;		represented by the variable, at the output of the 12-bit 
;		DAC on the 24x/24xx EVM. 
;				|~~~~~~~~~~~~~~~|
;	DAC_IPTR0	o------>|		|----->o  DAC0 (pin)
;	DAC_IPTR1	o------>|		|----->o  DAC1 (pin)
;	DAC_IPTR2	o------>| DAC_VIEW_DRV	|----->o  DAC2 (pin)
;	DAC_IPTR3	o------>|		|----->o  DAC3 (pin)
;				|_______________|
;
;	The input variables ( DAC_IPTR0,...etc) are pointers to Data RAM,
;	hence any Data RAM variable (in Q15 representation) can be output
;	to the DAC. Useful in Real-time mode to change DAC signals on the
;	"fly".
;
; Target: 'LF2407/F243/F240 EVM
;
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000	Release	Rev 1.0
;===========================================================================
;(To use this Module, copy this section to main system file)
;		.ref	DAC_VIEW_DRV,DAC_VIEW_DRV_INIT		; function call
;		.ref	DAC_IPTR0,DAC_IPTR1,DAC_IPTR2,DAC_IPTR3	; Inputs
;===========================================================================
;Module definitions for external reference.
		.def	DAC_VIEW_DRV,DAC_VIEW_DRV_INIT		; function call
		.def	DAC_IPTR0,DAC_IPTR1,DAC_IPTR2,DAC_IPTR3	; Inputs
;===========================================================================
		;.include	x24x_app.h

DAC_FLL_RES	.set	4095			; Note: DAC is 12bit res.
DAC_HLF_RES	.set	2047

dac_hlf_rng	.usect "dac_view",1
dac_fll_rng	.usect "dac_view",1
DAC_IPTR0	.usect "dac_view",1
DAC_IPTR1	.usect "dac_view",1
DAC_IPTR2	.usect "dac_view",1
DAC_IPTR3	.usect "dac_view",1
DAC_tmp0	.usect "dac_view",1

DAC_VIEW_DRV_INIT:
		LDP	#dac_hlf_rng
		SPLK	#DAC_HLF_RES,dac_hlf_rng
		SPLK	#DAC_FLL_RES,dac_fll_rng
		SPLK	#295h,DAC_IPTR0
		SPLK	#291h,DAC_IPTR1
		SPLK	#300h,DAC_IPTR2
		SPLK	#300h,DAC_IPTR3
		RET

DAC_VIEW_DRV:
;Convert Q15 input value to an absolute Q0 output to DAC0 channel
		SPM	1
		MAR	*,AR6
		LDP	#DAC_IPTR0
		LAR	AR6,DAC_IPTR0
		LT	*
		MPY	dac_hlf_rng		; Normalise to half range of DAC
		PAC				;
		ADDH	dac_hlf_rng		; offset by 1/2 DAC max value
		SACH	DAC_tmp0
		OUT	DAC_tmp0,PA0	; DAC0 o/p

;Convert Q15 input value to an absolute Q0 output to DAC1 channel
		LAR	AR6,DAC_IPTR1
		LT	*
		MPY	dac_hlf_rng		; Normalise to half range of DAC
		PAC				;
		ADDH	dac_hlf_rng		; offset by 1/2 DAC max value
		SACH	DAC_tmp0
		OUT	DAC_tmp0,PA1	;DAC1 o/p

;Convert Q15 input value to an absolute Q0 output to DAC2 channel
		LAR	AR6,DAC_IPTR2
		LT	*
		MPY	dac_hlf_rng		; Normalise to half range of DAC
		PAC				;
		ADDH	dac_hlf_rng		; offset by 1/2 DAC max value
		SACH	DAC_tmp0
		OUT	DAC_tmp0,PA2	;DAC2 o/p

;Convert Q15 input value to an absolute Q0 output to DAC3 channel
		LAR	AR6,DAC_IPTR3
		LT	*
		MPY	dac_hlf_rng		; Normalise to half range of DAC
		PAC				;
		ADDH	dac_hlf_rng		; offset by 1/2 DAC max value
		SACH	DAC_tmp0
		OUT	DAC_tmp0,PA3	; DAC3 o/p
;update DAC:
		OUT	DAC_tmp0,PA4	; here DAC_tmp0 is only a dummy.
		mar	*,AR1			; C requirement
		SPM	0			; C requirement
		RET