cs461x.h

iis s3c2410-uda1341语音系统的 开发

#define DREG_REGID_RA_BUS_LOW                   0x00000020
#define DREG_REGID_RA_BUS_HIGH                  0x00000038
#define DREG_REGID_YBUS_LOW                     0x00000050
#define DREG_REGID_YBUS_HIGH                    0x00000058
#define DREG_REGID_TRAP_0                       0x00000100
#define DREG_REGID_TRAP_1                       0x00000101
#define DREG_REGID_TRAP_2                       0x00000102
#define DREG_REGID_TRAP_3                       0x00000103
#define DREG_REGID_TRAP_4                       0x00000104
#define DREG_REGID_TRAP_5                       0x00000105
#define DREG_REGID_TRAP_6                       0x00000106
#define DREG_REGID_TRAP_7                       0x00000107
#define DREG_REGID_INDIRECT_ADDRESS             0x0000010E
#define DREG_REGID_TOP_OF_STACK                 0x0000010F
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_REGID_TRAP_8                       0x00000110
#define DREG_REGID_TRAP_9                       0x00000111
#define DREG_REGID_TRAP_10                      0x00000112
#define DREG_REGID_TRAP_11                      0x00000113
#define DREG_REGID_TRAP_12                      0x00000114
#define DREG_REGID_TRAP_13                      0x00000115
#define DREG_REGID_TRAP_14                      0x00000116
#define DREG_REGID_TRAP_15                      0x00000117
#define DREG_REGID_TRAP_16                      0x00000118
#define DREG_REGID_TRAP_17                      0x00000119
#define DREG_REGID_TRAP_18                      0x0000011A
#define DREG_REGID_TRAP_19                      0x0000011B
#define DREG_REGID_TRAP_20                      0x0000011C
#define DREG_REGID_TRAP_21                      0x0000011D
#define DREG_REGID_TRAP_22                      0x0000011E
#define DREG_REGID_TRAP_23                      0x0000011F
#endif
#endif
#define DREG_REGID_RSA0_LOW                     0x00000200
#define DREG_REGID_RSA0_HIGH                    0x00000201
#define DREG_REGID_RSA1_LOW                     0x00000202
#define DREG_REGID_RSA1_HIGH                    0x00000203
#define DREG_REGID_RSA2                         0x00000204
#define DREG_REGID_RSA3                         0x00000205
#define DREG_REGID_RSI0_LOW                     0x00000206
#define DREG_REGID_RSI0_HIGH                    0x00000207
#define DREG_REGID_RSI1                         0x00000208
#define DREG_REGID_RSI2                         0x00000209
#define DREG_REGID_SAGUSTATUS                   0x0000020A
#define DREG_REGID_RSCONFIG01_LOW               0x0000020B
#define DREG_REGID_RSCONFIG01_HIGH              0x0000020C
#define DREG_REGID_RSCONFIG23_LOW               0x0000020D
#define DREG_REGID_RSCONFIG23_HIGH              0x0000020E
#define DREG_REGID_RSDMA01E                     0x0000020F
#define DREG_REGID_RSDMA23E                     0x00000210
#define DREG_REGID_RSD0_LOW                     0x00000211
#define DREG_REGID_RSD0_HIGH                    0x00000212
#define DREG_REGID_RSD1_LOW                     0x00000213
#define DREG_REGID_RSD1_HIGH                    0x00000214
#define DREG_REGID_RSD2_LOW                     0x00000215
#define DREG_REGID_RSD2_HIGH                    0x00000216
#define DREG_REGID_RSD3_LOW                     0x00000217
#define DREG_REGID_RSD3_HIGH                    0x00000218
#define DREG_REGID_SRAR_HIGH                    0x0000021A
#define DREG_REGID_SRAR_LOW                     0x0000021B
#define DREG_REGID_DMA_STATE                    0x0000021C
#define DREG_REGID_CURRENT_DMA_STREAM           0x0000021D
#define DREG_REGID_NEXT_DMA_STREAM              0x0000021E
#define DREG_REGID_CPU_STATUS                   0x00000300
#define DREG_REGID_MAC_MODE                     0x00000301
#define DREG_REGID_STACK_AND_REPEAT             0x00000302
#define DREG_REGID_INDEX0                       0x00000304
#define DREG_REGID_INDEX1                       0x00000305
#define DREG_REGID_DMA_STATE_0_3                0x00000400
#define DREG_REGID_DMA_STATE_4_7                0x00000404
#define DREG_REGID_DMA_STATE_8_11               0x00000408
#define DREG_REGID_DMA_STATE_12_15              0x0000040C
#define DREG_REGID_DMA_STATE_16_19              0x00000410
#define DREG_REGID_DMA_STATE_20_23              0x00000414
#define DREG_REGID_DMA_STATE_24_27              0x00000418
#define DREG_REGID_DMA_STATE_28_31              0x0000041C
#define DREG_REGID_DMA_STATE_32_35              0x00000420
#define DREG_REGID_DMA_STATE_36_39              0x00000424
#define DREG_REGID_DMA_STATE_40_43              0x00000428
#define DREG_REGID_DMA_STATE_44_47              0x0000042C
#define DREG_REGID_DMA_STATE_48_51              0x00000430
#define DREG_REGID_DMA_STATE_52_55              0x00000434
#define DREG_REGID_DMA_STATE_56_59              0x00000438
#define DREG_REGID_DMA_STATE_60_63              0x0000043C
#define DREG_REGID_DMA_STATE_64_67              0x00000440
#define DREG_REGID_DMA_STATE_68_71              0x00000444
#define DREG_REGID_DMA_STATE_72_75              0x00000448
#define DREG_REGID_DMA_STATE_76_79              0x0000044C
#define DREG_REGID_DMA_STATE_80_83              0x00000450
#define DREG_REGID_DMA_STATE_84_87              0x00000454
#define DREG_REGID_DMA_STATE_88_91              0x00000458
#define DREG_REGID_DMA_STATE_92_95              0x0000045C
#define DREG_REGID_TRAP_SELECT                  0x00000500
#define DREG_REGID_TRAP_WRITE_0                 0x00000500
#define DREG_REGID_TRAP_WRITE_1                 0x00000501
#define DREG_REGID_TRAP_WRITE_2                 0x00000502
#define DREG_REGID_TRAP_WRITE_3                 0x00000503
#define DREG_REGID_TRAP_WRITE_4                 0x00000504
#define DREG_REGID_TRAP_WRITE_5                 0x00000505
#define DREG_REGID_TRAP_WRITE_6                 0x00000506
#define DREG_REGID_TRAP_WRITE_7                 0x00000507
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_REGID_TRAP_WRITE_8                 0x00000510
#define DREG_REGID_TRAP_WRITE_9                 0x00000511
#define DREG_REGID_TRAP_WRITE_10                0x00000512
#define DREG_REGID_TRAP_WRITE_11                0x00000513
#define DREG_REGID_TRAP_WRITE_12                0x00000514
#define DREG_REGID_TRAP_WRITE_13                0x00000515
#define DREG_REGID_TRAP_WRITE_14                0x00000516
#define DREG_REGID_TRAP_WRITE_15                0x00000517
#define DREG_REGID_TRAP_WRITE_16                0x00000518
#define DREG_REGID_TRAP_WRITE_17                0x00000519
#define DREG_REGID_TRAP_WRITE_18                0x0000051A
#define DREG_REGID_TRAP_WRITE_19                0x0000051B
#define DREG_REGID_TRAP_WRITE_20                0x0000051C
#define DREG_REGID_TRAP_WRITE_21                0x0000051D
#define DREG_REGID_TRAP_WRITE_22                0x0000051E
#define DREG_REGID_TRAP_WRITE_23                0x0000051F
#endif
#endif
#define DREG_REGID_MAC0_ACC0_LOW                0x00000600
#define DREG_REGID_MAC0_ACC1_LOW                0x00000601
#define DREG_REGID_MAC0_ACC2_LOW                0x00000602
#define DREG_REGID_MAC0_ACC3_LOW                0x00000603
#define DREG_REGID_MAC1_ACC0_LOW                0x00000604
#define DREG_REGID_MAC1_ACC1_LOW                0x00000605
#define DREG_REGID_MAC1_ACC2_LOW                0x00000606
#define DREG_REGID_MAC1_ACC3_LOW                0x00000607
#define DREG_REGID_MAC0_ACC0_MID                0x00000608
#define DREG_REGID_MAC0_ACC1_MID                0x00000609
#define DREG_REGID_MAC0_ACC2_MID                0x0000060A
#define DREG_REGID_MAC0_ACC3_MID                0x0000060B
#define DREG_REGID_MAC1_ACC0_MID                0x0000060C
#define DREG_REGID_MAC1_ACC1_MID                0x0000060D
#define DREG_REGID_MAC1_ACC2_MID                0x0000060E
#define DREG_REGID_MAC1_ACC3_MID                0x0000060F
#define DREG_REGID_MAC0_ACC0_HIGH               0x00000610
#define DREG_REGID_MAC0_ACC1_HIGH               0x00000611
#define DREG_REGID_MAC0_ACC2_HIGH               0x00000612
#define DREG_REGID_MAC0_ACC3_HIGH               0x00000613
#define DREG_REGID_MAC1_ACC0_HIGH               0x00000614
#define DREG_REGID_MAC1_ACC1_HIGH               0x00000615
#define DREG_REGID_MAC1_ACC2_HIGH               0x00000616
#define DREG_REGID_MAC1_ACC3_HIGH               0x00000617
#define DREG_REGID_RSHOUT_LOW                   0x00000620
#define DREG_REGID_RSHOUT_MID                   0x00000628
#define DREG_REGID_RSHOUT_HIGH                  0x00000630

/*
 *  The following defines are for the flags in the DMA stream requestor write
 */
#define DSRWP_DSR_MASK                          0x0000000F
#define DSRWP_DSR_BG_RQ                         0x00000001
#define DSRWP_DSR_PRIORITY_MASK                 0x00000006
#define DSRWP_DSR_PRIORITY_0                    0x00000000
#define DSRWP_DSR_PRIORITY_1                    0x00000002
#define DSRWP_DSR_PRIORITY_2                    0x00000004
#define DSRWP_DSR_PRIORITY_3                    0x00000006
#define DSRWP_DSR_RQ_PENDING                    0x00000008

/*
 *  The following defines are for the flags in the trap write port register.
 */
#define TWPR_TW_MASK                            0x0000FFFF
#define TWPR_TW_SHIFT                           0

/*
 *  The following defines are for the flags in the stack pointer write
 *  register.
 */
#define SPWR_STKP_MASK                          0x0000000F
#define SPWR_STKP_SHIFT                         0

/*
 *  The following defines are for the flags in the SP interrupt register.
 */
#define SPIR_FRI                                0x00000001
#define SPIR_DOI                                0x00000002
#define SPIR_GPI2                               0x00000004
#define SPIR_GPI3                               0x00000008
#define SPIR_IP0                                0x00000010
#define SPIR_IP1                                0x00000020
#define SPIR_IP2                                0x00000040
#define SPIR_IP3                                0x00000080

/*
 *  The following defines are for the flags in the functional group 1 register.
 */
#define FGR1_F1S_MASK                           0x0000FFFF
#define FGR1_F1S_SHIFT                          0

/*
 *  The following defines are for the flags in the SP clock status register.
 */
#define SPCS_FRI                                0x00000001
#define SPCS_DOI                                0x00000002
#define SPCS_GPI2                               0x00000004
#define SPCS_GPI3                               0x00000008
#define SPCS_IP0                                0x00000010
#define SPCS_IP1                                0x00000020
#define SPCS_IP2                                0x00000040
#define SPCS_IP3                                0x00000080
#define SPCS_SPRUN                              0x00000100
#define SPCS_SLEEP                              0x00000200
#define SPCS_FG                                 0x00000400
#define SPCS_ORUN                               0x00000800
#define SPCS_IRQ                                0x00001000
#define SPCS_FGN_MASK                           0x0000E000
#define SPCS_FGN_SHIFT                          13

/*
 *  The following defines are for the flags in the SP DMA requestor status
 *  register.
 */
#define SDSR_DCS_MASK                           0x000000FF
#define SDSR_DCS_SHIFT                          0
#define SDSR_DCS_NONE                           0x00000007

/*
 *  The following defines are for the flags in the frame timer register.
 */
#define FRMT_FTV_MASK                           0x0000FFFF
#define FRMT_FTV_SHIFT                          0

/*
 *  The following defines are for the flags in the frame timer current count
 *  register.
 */
#define FRCC_FCC_MASK                           0x0000FFFF
#define FRCC_FCC_SHIFT                          0

/*
 *  The following defines are for the flags in the frame timer save count
 *  register.
 */
#define FRSC_FCS_MASK                           0x0000FFFF
#define FRSC_FCS_SHIFT                          0

/*
 *  The following define the various flags stored in the scatter/gather
 *  descriptors.
 */
#define DMA_SG_NEXT_ENTRY_MASK                  0x00000FF8
#define DMA_SG_SAMPLE_END_MASK                  0x0FFF0000
#define DMA_SG_SAMPLE_END_FLAG                  0x10000000
#define DMA_SG_LOOP_END_FLAG                    0x20000000
#define DMA_SG_SIGNAL_END_FLAG                  0x40000000
#define DMA_SG_SIGNAL_PAGE_FLAG                 0x80000000
#define DMA_SG_NEXT_ENTRY_SHIFT                 3
#define DMA_SG_SAMPLE_END_SHIFT                 16

/*
 *  The following define the offsets of the fields within the on-chip generic
 *  DMA requestor.
 */
#define DMA_RQ_CONTROL1                         0x00000000
#define DMA_RQ_CONTROL2                         0x00000004
#define DMA_RQ_SOURCE_ADDR                      0x00000008
#define DMA_RQ_DESTINATION_ADDR                 0x0000000C
#define DMA_RQ_NEXT_PAGE_ADDR                   0x00000010
#define DMA_RQ_NEXT_PAGE_SGDESC                 0x00000014
#define DMA_RQ_LOOP_START_ADDR                  0x00000018
#define DMA_RQ_POST_LOOP_ADDR                   0x0000001C
#define DMA_RQ_PAGE_MAP_ADDR                    0x00000020

/*
 *  The following defines are for the flags in the first control word of the
 *  on-chip generic DMA requestor.
 */
#define DMA_RQ_C1_COUNT_MASK                    0x000003FF
#define DMA_RQ_C1_DESTINATION_SCATTER           0x00001000
#define DMA_RQ_C1_SOURCE_GATHER                 0x00002000
#define DMA_RQ_C1_DONE_FLAG                     0x00004000
#define DMA_RQ_C1_OPTIMIZE_STATE                0x00008000
#define DMA_RQ_C1_SAMPLE_END_STATE_MASK         0x00030000
#define DMA_RQ_C1_FULL_PAGE                     0x00000000
#define DMA_RQ_C1_BEFORE_SAMPLE_END             0x00010000
#define DMA_RQ_C1_PAGE_MAP_ERROR                0x00020000
#define DMA_RQ_C1_AT_SAMPLE_END                 0x00030000
#define DMA_RQ_C1_LOOP_END_STATE_MASK           0x000C0000
#define DMA_RQ_C1_NOT_LOOP_END                  0x00000000
#define DMA_RQ_C1_BEFORE_LOOP_END               0x00040000
#define DMA_RQ_C1_2PAGE_LOOP_BEGIN              0x00080000
#define DMA_RQ_C1_LOOP_BEGIN                    0x000C0000
#define DMA_RQ_C1_PAGE_MAP_MASK                 0x00300000
#define DMA_RQ_C1_PM_NONE_PENDING               0x00000000
#define DMA_RQ_C1_PM_NEXT_PENDING               0x00100000
#define DMA_RQ_C1_PM_RESERVED                   0x00200000
#define DMA_RQ_C1_PM_LOOP_NEXT_PENDING          0x00300000
#define DMA_RQ_C1_WRITEBACK_DEST_FLAG           0x00400000
#define DMA_RQ_C1_WRITEBACK_SRC_FLAG            0x00800000
#define DMA_RQ_C1_DEST_SIZE_MASK                0x07000000
#define DMA_RQ_C1_DEST_LINEAR                   0x00000000
#define DMA_RQ_C1_DEST_MOD16                    0x01000000
#define DMA_RQ_C1_DEST_MOD32                    0x02000000
#define DMA_RQ_C1_DEST_MOD64                    0x03000000
#define DMA_RQ_C1_DEST_MOD128                   0x04000000
#define DMA_RQ_C1_DEST_MOD256                   0x05000000
#define DMA_RQ_C1_DEST_MOD512