cs461x.h

iis s3c2410-uda1341语音系统的 开发

 *  The following defines are for the flags in the serial port 7 configuration
 *  register.
 */
#ifndef NO_CS4612
#define SERC7_ASDI2EN                           0x00000001
#define SERC7_POSILB                            0x00000002
#define SERC7_SIPOLB                            0x00000004
#define SERC7_SOSILB                            0x00000008
#define SERC7_SISOLB                            0x00000010
#endif

/*
 *  The following defines are for the flags in the serial port AC link
 *  configuration register.
 */
#ifndef NO_CS4612
#define SERACC_CODEC_TYPE_MASK                  0x00000001
#define SERACC_CODEC_TYPE_1_03                  0x00000000
#define SERACC_CODEC_TYPE_2_0                   0x00000001
#define SERACC_TWO_CODECS                       0x00000002
#define SERACC_MDM                              0x00000004
#define SERACC_HSP                              0x00000008
#endif

/*
 *  The following defines are for the flags in the AC97 control register 2.
 */
#ifndef NO_CS4612
#define ACCTL2_RSTN                             0x00000001
#define ACCTL2_ESYN                             0x00000002
#define ACCTL2_VFRM                             0x00000004
#define ACCTL2_DCV                              0x00000008
#define ACCTL2_CRW                              0x00000010
#define ACCTL2_ASYN                             0x00000020
#endif

/*
 *  The following defines are for the flags in the AC97 status register 2.
 */
#ifndef NO_CS4612
#define ACSTS2_CRDY                             0x00000001
#define ACSTS2_VSTS                             0x00000002
#endif

/*
 *  The following defines are for the flags in the AC97 output slot valid
 *  register 2.
 */
#ifndef NO_CS4612
#define ACOSV2_SLV3                             0x00000001
#define ACOSV2_SLV4                             0x00000002
#define ACOSV2_SLV5                             0x00000004
#define ACOSV2_SLV6                             0x00000008
#define ACOSV2_SLV7                             0x00000010
#define ACOSV2_SLV8                             0x00000020
#define ACOSV2_SLV9                             0x00000040
#define ACOSV2_SLV10                            0x00000080
#define ACOSV2_SLV11                            0x00000100
#define ACOSV2_SLV12                            0x00000200
#endif

/*
 *  The following defines are for the flags in the AC97 command address
 *  register 2.
 */
#ifndef NO_CS4612
#define ACCAD2_CI_MASK                          0x0000007F
#define ACCAD2_CI_SHIFT                         0
#endif

/*
 *  The following defines are for the flags in the AC97 command data register
 *  2.
 */
#ifndef NO_CS4612
#define ACCDA2_CD_MASK                          0x0000FFFF
#define ACCDA2_CD_SHIFT                         0  
#endif

/*
 *  The following defines are for the flags in the AC97 input slot valid
 *  register 2.
 */
#ifndef NO_CS4612
#define ACISV2_ISV3                             0x00000001
#define ACISV2_ISV4                             0x00000002
#define ACISV2_ISV5                             0x00000004
#define ACISV2_ISV6                             0x00000008
#define ACISV2_ISV7                             0x00000010
#define ACISV2_ISV8                             0x00000020
#define ACISV2_ISV9                             0x00000040
#define ACISV2_ISV10                            0x00000080
#define ACISV2_ISV11                            0x00000100
#define ACISV2_ISV12                            0x00000200
#endif

/*
 *  The following defines are for the flags in the AC97 status address
 *  register 2.
 */
#ifndef NO_CS4612
#define ACSAD2_SI_MASK                          0x0000007F
#define ACSAD2_SI_SHIFT                         0
#endif

/*
 *  The following defines are for the flags in the AC97 status data register 2.
 */
#ifndef NO_CS4612
#define ACSDA2_SD_MASK                          0x0000FFFF
#define ACSDA2_SD_SHIFT                         0
#endif

/*
 *  The following defines are for the flags in the I/O trap address and control
 *  registers (all 12).
 */
#ifndef NO_CS4612
#define IOTAC_SA_MASK                           0x0000FFFF
#define IOTAC_MSK_MASK                          0x000F0000
#define IOTAC_IODC_MASK                         0x06000000
#define IOTAC_IODC_16_BIT                       0x00000000
#define IOTAC_IODC_10_BIT                       0x02000000
#define IOTAC_IODC_12_BIT                       0x04000000
#define IOTAC_WSPI                              0x08000000
#define IOTAC_RSPI                              0x10000000
#define IOTAC_WSE                               0x20000000
#define IOTAC_WE                                0x40000000
#define IOTAC_RE                                0x80000000
#define IOTAC_SA_SHIFT                          0
#define IOTAC_MSK_SHIFT                         16
#endif

/*
 *  The following defines are for the flags in the I/O trap fast read registers
 *  (all 8).
 */
#ifndef NO_CS4612
#define IOTFR_D_MASK                            0x0000FFFF
#define IOTFR_A_MASK                            0x000F0000
#define IOTFR_R_MASK                            0x0F000000
#define IOTFR_ALL                               0x40000000
#define IOTFR_VL                                0x80000000
#define IOTFR_D_SHIFT                           0
#define IOTFR_A_SHIFT                           16
#define IOTFR_R_SHIFT                           24
#endif

/*
 *  The following defines are for the flags in the I/O trap FIFO register.
 */
#ifndef NO_CS4612
#define IOTFIFO_BA_MASK                         0x00003FFF
#define IOTFIFO_S_MASK                          0x00FF0000
#define IOTFIFO_OF                              0x40000000
#define IOTFIFO_SPIOF                           0x80000000
#define IOTFIFO_BA_SHIFT                        0
#define IOTFIFO_S_SHIFT                         16
#endif

/*
 *  The following defines are for the flags in the I/O trap retry read data
 *  register.
 */
#ifndef NO_CS4612
#define IOTRRD_D_MASK                           0x0000FFFF
#define IOTRRD_RDV                              0x80000000
#define IOTRRD_D_SHIFT                          0
#endif

/*
 *  The following defines are for the flags in the I/O trap FIFO pointer
 *  register.
 */
#ifndef NO_CS4612
#define IOTFP_CA_MASK                           0x00003FFF
#define IOTFP_PA_MASK                           0x3FFF0000
#define IOTFP_CA_SHIFT                          0
#define IOTFP_PA_SHIFT                          16
#endif

/*
 *  The following defines are for the flags in the I/O trap control register.
 */
#ifndef NO_CS4612
#define IOTCR_ITD                               0x00000001
#define IOTCR_HRV                               0x00000002
#define IOTCR_SRV                               0x00000004
#define IOTCR_DTI                               0x00000008
#define IOTCR_DFI                               0x00000010
#define IOTCR_DDP                               0x00000020
#define IOTCR_JTE                               0x00000040
#define IOTCR_PPE                               0x00000080
#endif

/*
 *  The following defines are for the flags in the direct PCI data register.
 */
#ifndef NO_CS4612
#define DPCID_D_MASK                            0xFFFFFFFF
#define DPCID_D_SHIFT                           0
#endif

/*
 *  The following defines are for the flags in the direct PCI address register.
 */
#ifndef NO_CS4612
#define DPCIA_A_MASK                            0xFFFFFFFF
#define DPCIA_A_SHIFT                           0
#endif

/*
 *  The following defines are for the flags in the direct PCI command register.
 */
#ifndef NO_CS4612
#define DPCIC_C_MASK                            0x0000000F
#define DPCIC_C_IOREAD                          0x00000002
#define DPCIC_C_IOWRITE                         0x00000003
#define DPCIC_BE_MASK                           0x000000F0
#endif

/*
 *  The following defines are for the flags in the PC/PCI request register.
 */
#ifndef NO_CS4612
#define PCPCIR_RDC_MASK                         0x00000007
#define PCPCIR_C_MASK                           0x00007000
#define PCPCIR_REQ                              0x00008000
#define PCPCIR_RDC_SHIFT                        0
#define PCPCIR_C_SHIFT                          12
#endif

/*
 *  The following defines are for the flags in the PC/PCI grant register.
 */ 
#ifndef NO_CS4612
#define PCPCIG_GDC_MASK                         0x00000007
#define PCPCIG_VL                               0x00008000
#define PCPCIG_GDC_SHIFT                        0
#endif

/*
 *  The following defines are for the flags in the PC/PCI master enable
 *  register.
 */
#ifndef NO_CS4612
#define PCPCIEN_EN                              0x00000001
#endif

/*
 *  The following defines are for the flags in the extended PCI power
 *  management control register.
 */
#ifndef NO_CS4612
#define EPCIPMC_GWU                             0x00000001
#define EPCIPMC_FSPC                            0x00000002
#endif 

/*
 *  The following defines are for the flags in the SP control register.
 */
#define SPCR_RUN                                0x00000001
#define SPCR_STPFR                              0x00000002
#define SPCR_RUNFR                              0x00000004
#define SPCR_TICK                               0x00000008
#define SPCR_DRQEN                              0x00000020
#define SPCR_RSTSP                              0x00000040
#define SPCR_OREN                               0x00000080
#ifndef NO_CS4612
#define SPCR_PCIINT                             0x00000100
#define SPCR_OINTD                              0x00000200
#define SPCR_CRE                                0x00008000
#endif

/*
 *  The following defines are for the flags in the debug index register.
 */
#define DREG_REGID_MASK                         0x0000007F
#define DREG_DEBUG                              0x00000080
#define DREG_RGBK_MASK                          0x00000700
#define DREG_TRAP                               0x00000800
#if !defined(NO_CS4612)
#if !defined(NO_CS4615)
#define DREG_TRAPX                              0x00001000
#endif
#endif
#define DREG_REGID_SHIFT                        0
#define DREG_RGBK_SHIFT                         8
#define DREG_RGBK_REGID_MASK                    0x0000077F
#define DREG_REGID_R0                           0x00000010
#define DREG_REGID_R1                           0x00000011
#define DREG_REGID_R2                           0x00000012
#define DREG_REGID_R3                           0x00000013
#define DREG_REGID_R4                           0x00000014
#define DREG_REGID_R5                           0x00000015
#define DREG_REGID_R6                           0x00000016
#define DREG_REGID_R7                           0x00000017
#define DREG_REGID_R8                           0x00000018
#define DREG_REGID_R9                           0x00000019
#define DREG_REGID_RA                           0x0000001A
#define DREG_REGID_RB                           0x0000001B
#define DREG_REGID_RC                           0x0000001C
#define DREG_REGID_RD                           0x0000001D
#define DREG_REGID_RE                           0x0000001E
#define DREG_REGID_RF                           0x0000001F