cs461x.h

iis s3c2410-uda1341语音系统的 开发

#define HDAR_MEMID_OMNI_MEM                     0x000E0000
#define HDAR_END                                0x40000000
#define HDAR_ERR                                0x80000000

/*
 *  The following defines are for the flags in the host DMA control register.
 */
#define HDMR_AC_MASK                            0x0000F000
#define HDMR_AC_8_16                            0x00001000
#define HDMR_AC_M_S                             0x00002000
#define HDMR_AC_B_L                             0x00004000
#define HDMR_AC_S_U                             0x00008000

/*
 *  The following defines are for the flags in the host DMA control register.
 */
#define HDCR_COUNT_MASK                         0x000003FF
#define HDCR_DONE                               0x00004000
#define HDCR_OPT                                0x00008000
#define HDCR_WBD                                0x00400000
#define HDCR_WBS                                0x00800000
#define HDCR_DMS_MASK                           0x07000000
#define HDCR_DMS_LINEAR                         0x00000000
#define HDCR_DMS_16_DWORDS                      0x01000000
#define HDCR_DMS_32_DWORDS                      0x02000000
#define HDCR_DMS_64_DWORDS                      0x03000000
#define HDCR_DMS_128_DWORDS                     0x04000000
#define HDCR_DMS_256_DWORDS                     0x05000000
#define HDCR_DMS_512_DWORDS                     0x06000000
#define HDCR_DMS_1024_DWORDS                    0x07000000
#define HDCR_DH                                 0x08000000
#define HDCR_SMS_MASK                           0x70000000
#define HDCR_SMS_LINEAR                         0x00000000
#define HDCR_SMS_16_DWORDS                      0x10000000
#define HDCR_SMS_32_DWORDS                      0x20000000
#define HDCR_SMS_64_DWORDS                      0x30000000
#define HDCR_SMS_128_DWORDS                     0x40000000
#define HDCR_SMS_256_DWORDS                     0x50000000
#define HDCR_SMS_512_DWORDS                     0x60000000
#define HDCR_SMS_1024_DWORDS                    0x70000000
#define HDCR_SH                                 0x80000000
#define HDCR_COUNT_SHIFT                        0

/*
 *  The following defines are for the flags in the performance monitor control
 *  register.
 */
#define PFMC_C1SS_MASK                          0x0000001F
#define PFMC_C1EV                               0x00000020
#define PFMC_C1RS                               0x00008000
#define PFMC_C2SS_MASK                          0x001F0000
#define PFMC_C2EV                               0x00200000
#define PFMC_C2RS                               0x80000000
#define PFMC_C1SS_SHIFT                         0
#define PFMC_C2SS_SHIFT                         16
#define PFMC_BUS_GRANT                          0
#define PFMC_GRANT_AFTER_REQ                    1
#define PFMC_TRANSACTION                        2
#define PFMC_DWORD_TRANSFER                     3
#define PFMC_SLAVE_READ                         4
#define PFMC_SLAVE_WRITE                        5
#define PFMC_PREEMPTION                         6
#define PFMC_DISCONNECT_RETRY                   7
#define PFMC_INTERRUPT                          8
#define PFMC_BUS_OWNERSHIP                      9
#define PFMC_TRANSACTION_LAG                    10
#define PFMC_PCI_CLOCK                          11
#define PFMC_SERIAL_CLOCK                       12
#define PFMC_SP_CLOCK                           13

/*
 *  The following defines are for the flags in the performance counter value 1
 *  register.
 */
#define PFCV1_PC1V_MASK                         0xFFFFFFFF
#define PFCV1_PC1V_SHIFT                        0

/*
 *  The following defines are for the flags in the performance counter value 2
 *  register.
 */
#define PFCV2_PC2V_MASK                         0xFFFFFFFF
#define PFCV2_PC2V_SHIFT                        0

/*
 *  The following defines are for the flags in the clock control register 1.
 */
#define CLKCR1_OSCS                             0x00000001
#define CLKCR1_OSCP                             0x00000002
#define CLKCR1_PLLSS_MASK                       0x0000000C
#define CLKCR1_PLLSS_SERIAL                     0x00000000
#define CLKCR1_PLLSS_CRYSTAL                    0x00000004
#define CLKCR1_PLLSS_PCI                        0x00000008
#define CLKCR1_PLLSS_RESERVED                   0x0000000C
#define CLKCR1_PLLP                             0x00000010
#define CLKCR1_SWCE                             0x00000020
#define CLKCR1_PLLOS                            0x00000040

/*
 *  The following defines are for the flags in the clock control register 2.
 */
#define CLKCR2_PDIVS_MASK                       0x0000000F
#define CLKCR2_PDIVS_1                          0x00000001
#define CLKCR2_PDIVS_2                          0x00000002
#define CLKCR2_PDIVS_4                          0x00000004
#define CLKCR2_PDIVS_7                          0x00000007
#define CLKCR2_PDIVS_8                          0x00000008
#define CLKCR2_PDIVS_16                         0x00000000

/*
 *  The following defines are for the flags in the PLL multiplier register.
 */
#define PLLM_MASK                               0x000000FF
#define PLLM_SHIFT                              0

/*
 *  The following defines are for the flags in the PLL capacitor coefficient
 *  register.
 */
#define PLLCC_CDR_MASK                          0x00000007
#ifndef NO_CS4610
#define PLLCC_CDR_240_350_MHZ                   0x00000000
#define PLLCC_CDR_184_265_MHZ                   0x00000001
#define PLLCC_CDR_144_205_MHZ                   0x00000002
#define PLLCC_CDR_111_160_MHZ                   0x00000003
#define PLLCC_CDR_87_123_MHZ                    0x00000004
#define PLLCC_CDR_67_96_MHZ                     0x00000005
#define PLLCC_CDR_52_74_MHZ                     0x00000006
#define PLLCC_CDR_45_58_MHZ                     0x00000007
#endif
#ifndef NO_CS4612
#define PLLCC_CDR_271_398_MHZ                   0x00000000
#define PLLCC_CDR_227_330_MHZ                   0x00000001
#define PLLCC_CDR_167_239_MHZ                   0x00000002
#define PLLCC_CDR_150_215_MHZ                   0x00000003
#define PLLCC_CDR_107_154_MHZ                   0x00000004
#define PLLCC_CDR_98_140_MHZ                    0x00000005
#define PLLCC_CDR_73_104_MHZ                    0x00000006
#define PLLCC_CDR_63_90_MHZ                     0x00000007
#endif
#define PLLCC_LPF_MASK                          0x000000F8
#ifndef NO_CS4610
#define PLLCC_LPF_23850_60000_KHZ               0x00000000
#define PLLCC_LPF_7960_26290_KHZ                0x00000008
#define PLLCC_LPF_4160_10980_KHZ                0x00000018
#define PLLCC_LPF_1740_4580_KHZ                 0x00000038
#define PLLCC_LPF_724_1910_KHZ                  0x00000078
#define PLLCC_LPF_317_798_KHZ                   0x000000F8
#endif
#ifndef NO_CS4612
#define PLLCC_LPF_25580_64530_KHZ               0x00000000
#define PLLCC_LPF_14360_37270_KHZ               0x00000008
#define PLLCC_LPF_6100_16020_KHZ                0x00000018
#define PLLCC_LPF_2540_6690_KHZ                 0x00000038
#define PLLCC_LPF_1050_2780_KHZ                 0x00000078
#define PLLCC_LPF_450_1160_KHZ                  0x000000F8
#endif

/*
 *  The following defines are for the flags in the feature reporting register.
 */
#define FRR_FAB_MASK                            0x00000003
#define FRR_MASK_MASK                           0x0000001C
#ifdef NO_CS4612
#define FRR_CFOP_MASK                           0x000000E0
#else
#define FRR_CFOP_MASK                           0x00000FE0
#endif
#define FRR_CFOP_NOT_DVD                        0x00000020
#define FRR_CFOP_A3D                            0x00000040
#define FRR_CFOP_128_PIN                        0x00000080
#ifndef NO_CS4612
#define FRR_CFOP_CS4280                         0x00000800
#endif
#define FRR_FAB_SHIFT                           0
#define FRR_MASK_SHIFT                          2
#define FRR_CFOP_SHIFT                          5

/*
 *  The following defines are for the flags in the configuration load 1
 *  register.
 */
#define CFL1_CLOCK_SOURCE_MASK                  0x00000003
#define CFL1_CLOCK_SOURCE_CS423X                0x00000000
#define CFL1_CLOCK_SOURCE_AC97                  0x00000001
#define CFL1_CLOCK_SOURCE_CRYSTAL               0x00000002
#define CFL1_CLOCK_SOURCE_DUAL_AC97             0x00000003
#define CFL1_VALID_DATA_MASK                    0x000000FF

/*
 *  The following defines are for the flags in the configuration load 2
 *  register.
 */
#define CFL2_VALID_DATA_MASK                    0x000000FF

/*
 *  The following defines are for the flags in the serial port master control
 *  register 1.
 */
#define SERMC1_MSPE                             0x00000001
#define SERMC1_PTC_MASK                         0x0000000E
#define SERMC1_PTC_CS423X                       0x00000000
#define SERMC1_PTC_AC97                         0x00000002
#define SERMC1_PTC_DAC                          0x00000004
#define SERMC1_PLB                              0x00000010
#define SERMC1_XLB                              0x00000020

/*
 *  The following defines are for the flags in the serial port master control
 *  register 2.
 */
#define SERMC2_LROE                             0x00000001
#define SERMC2_MCOE                             0x00000002
#define SERMC2_MCDIV                            0x00000004

/*
 *  The following defines are for the flags in the serial port 1 configuration
 *  register.
 */
#define SERC1_SO1EN                             0x00000001
#define SERC1_SO1F_MASK                         0x0000000E
#define SERC1_SO1F_CS423X                       0x00000000
#define SERC1_SO1F_AC97                         0x00000002
#define SERC1_SO1F_DAC                          0x00000004
#define SERC1_SO1F_SPDIF                        0x00000006

/*
 *  The following defines are for the flags in the serial port 2 configuration
 *  register.
 */
#define SERC2_SI1EN                             0x00000001
#define SERC2_SI1F_MASK                         0x0000000E
#define SERC2_SI1F_CS423X                       0x00000000
#define SERC2_SI1F_AC97                         0x00000002
#define SERC2_SI1F_ADC                          0x00000004
#define SERC2_SI1F_SPDIF                        0x00000006

/*
 *  The following defines are for the flags in the serial port 3 configuration
 *  register.
 */
#define SERC3_SO2EN                             0x00000001
#define SERC3_SO2F_MASK                         0x00000006
#define SERC3_SO2F_DAC                          0x00000000
#define SERC3_SO2F_SPDIF                        0x00000002

/*
 *  The following defines are for the flags in the serial port 4 configuration
 *  register.
 */
#define SERC4_SO3EN                             0x00000001
#define SERC4_SO3F_MASK                         0x00000006
#define SERC4_SO3F_DAC                          0x00000000
#define SERC4_SO3F_SPDIF                        0x00000002

/*
 *  The following defines are for the flags in the serial port 5 configuration
 *  register.
 */
#define SERC5_SI2EN                             0x00000001
#define SERC5_SI2F_MASK                         0x00000006
#define SERC5_SI2F_ADC                          0x00000000
#define SERC5_SI2F_SPDIF                        0x00000002

/*
 *  The following defines are for the flags in the serial port backdoor sample
 *  pointer register.
 */
#define SERBSP_FSP_MASK                         0x0000000F
#define SERBSP_FSP_SHIFT                        0

/*
 *  The following defines are for the flags in the serial port backdoor status
 *  register.
 */
#define SERBST_RRDY                             0x00000001
#define SERBST_WBSY                             0x00000002

/*
 *  The following defines are for the flags in the serial port backdoor command
 *  register.
 */
#define SERBCM_RDC                              0x00000001
#define SERBCM_WRC                              0x00000002

/*
 *  The following defines are for the flags in the serial port backdoor address
 *  register.
 */
#ifdef NO_CS4612
#define SERBAD_FAD_MASK                         0x000000FF
#else
#define SERBAD_FAD_MASK                         0x000001FF
#endif
#define SERBAD_FAD_SHIFT                        0

/*
 *  The following defines are for the flags in the serial port backdoor
 *  configuration register.
 */
#define SERBCF_HBP                              0x00000001

/*
 *  The following defines are for the flags in the serial port backdoor write
 *  port register.