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<p><a href="nasmdoca.html">Appendix A: Ndisasm</a><br>
<a href="nasmdoca.html#section-A.1">Section A.1: Introduction</a><br>
<a href="nasmdoca.html#section-A.2">Section A.2: Getting Started: Installation</a><br>
<a href="nasmdoca.html#section-A.3">Section A.3: Running NDISASM</a><br>
<a href="nasmdoca.html#section-A.3.1">Section A.3.1: COM Files: Specifying an Origin</a><br>
<a href="nasmdoca.html#section-A.3.2">Section A.3.2: Code Following Data: Synchronisation</a><br>
<a href="nasmdoca.html#section-A.3.3">Section A.3.3: Mixed Code and Data: Automatic (Intelligent) Synchronisation </a><br>
<a href="nasmdoca.html#section-A.3.4">Section A.3.4: Other Options</a><br>
<a href="nasmdoca.html#section-A.4">Section A.4: Bugs and Improvements</a><br>
<p><a href="nasmdocb.html">Appendix B: x86 Instruction Reference</a><br>
<a href="nasmdocb.html#section-B.1">Section B.1: Key to Operand Specifications</a><br>
<a href="nasmdocb.html#section-B.2">Section B.2: Key to Opcode Descriptions</a><br>
<a href="nasmdocb.html#section-B.2.1">Section B.2.1: Register Values</a><br>
<a href="nasmdocb.html#section-B.2.2">Section B.2.2: Condition Codes</a><br>
<a href="nasmdocb.html#section-B.2.3">Section B.2.3: SSE Condition Predicates</a><br>
<a href="nasmdocb.html#section-B.2.4">Section B.2.4: Status Flags</a><br>
<a href="nasmdocb.html#section-B.2.5">Section B.2.5: Effective Address Encoding: ModR/M and SIB</a><br>
<a href="nasmdocb.html#section-B.3">Section B.3: Key to Instruction Flags</a><br>
<a href="nasmdocb.html#section-B.4">Section B.4: x86 Instruction Set</a><br>
<a href="nasmdocb.html#section-B.4.1">Section B.4.1: <code><nobr>AAA</nobr></code>, <code><nobr>AAS</nobr></code>, <code><nobr>AAM</nobr></code>, <code><nobr>AAD</nobr></code>: ASCII Adjustments</a><br>
<a href="nasmdocb.html#section-B.4.2">Section B.4.2: <code><nobr>ADC</nobr></code>: Add with Carry</a><br>
<a href="nasmdocb.html#section-B.4.3">Section B.4.3: <code><nobr>ADD</nobr></code>: Add Integers</a><br>
<a href="nasmdocb.html#section-B.4.4">Section B.4.4: <code><nobr>ADDPD</nobr></code>: ADD Packed Double-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.5">Section B.4.5: <code><nobr>ADDPS</nobr></code>: ADD Packed Single-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.6">Section B.4.6: <code><nobr>ADDSD</nobr></code>: ADD Scalar Double-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.7">Section B.4.7: <code><nobr>ADDSS</nobr></code>: ADD Scalar Single-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.8">Section B.4.8: <code><nobr>AND</nobr></code>: Bitwise AND</a><br>
<a href="nasmdocb.html#section-B.4.9">Section B.4.9: <code><nobr>ANDNPD</nobr></code>: Bitwise Logical AND NOT of Packed Double-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.10">Section B.4.10: <code><nobr>ANDNPS</nobr></code>: Bitwise Logical AND NOT of Packed Single-Precision FP Values</a><br>
<a href="nasmdocb.html#section-B.4.11">Section B.4.11: <code><nobr>ANDPD</nobr></code>: Bitwise Logical AND For Single FP</a><br>
<a href="nasmdocb.html#section-B.4.12">Section B.4.12: <code><nobr>ANDPS</nobr></code>: Bitwise Logical AND For Single FP</a><br>
<a href="nasmdocb.html#section-B.4.13">Section B.4.13: <code><nobr>ARPL</nobr></code>: Adjust RPL Field of Selector</a><br>
<a href="nasmdocb.html#section-B.4.14">Section B.4.14: <code><nobr>BOUND</nobr></code>: Check Array Index against Bounds</a><br>
<a href="nasmdocb.html#section-B.4.15">Section B.4.15: <code><nobr>BSF</nobr></code>, <code><nobr>BSR</nobr></code>: Bit Scan</a><br>
<a href="nasmdocb.html#section-B.4.16">Section B.4.16: <code><nobr>BSWAP</nobr></code>: Byte Swap</a><br>
<a href="nasmdocb.html#section-B.4.17">Section B.4.17: <code><nobr>BT</nobr></code>, <code><nobr>BTC</nobr></code>, <code><nobr>BTR</nobr></code>, <code><nobr>BTS</nobr></code>: Bit Test</a><br>
<a href="nasmdocb.html#section-B.4.18">Section B.4.18: <code><nobr>CALL</nobr></code>: Call Subroutine</a><br>
<a href="nasmdocb.html#section-B.4.19">Section B.4.19: <code><nobr>CBW</nobr></code>, <code><nobr>CWD</nobr></code>, <code><nobr>CDQ</nobr></code>, <code><nobr>CWDE</nobr></code>: Sign Extensions</a><br>
<a href="nasmdocb.html#section-B.4.20">Section B.4.20: <code><nobr>CLC</nobr></code>, <code><nobr>CLD</nobr></code>, <code><nobr>CLI</nobr></code>, <code><nobr>CLTS</nobr></code>: Clear Flags</a><br>
<a href="nasmdocb.html#section-B.4.21">Section B.4.21: <code><nobr>CLFLUSH</nobr></code>: Flush Cache Line</a><br>
<a href="nasmdocb.html#section-B.4.22">Section B.4.22: <code><nobr>CMC</nobr></code>: Complement Carry Flag</a><br>
<a href="nasmdocb.html#section-B.4.23">Section B.4.23: <code><nobr>CMOVcc</nobr></code>: Conditional Move</a><br>
<a href="nasmdocb.html#section-B.4.24">Section B.4.24: <code><nobr>CMP</nobr></code>: Compare Integers</a><br>
<a href="nasmdocb.html#section-B.4.25">Section B.4.25: <code><nobr>CMPccPD</nobr></code>: Packed Double-Precision FP Compare        </a><br>
<a href="nasmdocb.html#section-B.4.26">Section B.4.26: <code><nobr>CMPccPS</nobr></code>: Packed Single-Precision FP Compare        </a><br>
<a href="nasmdocb.html#section-B.4.27">Section B.4.27: <code><nobr>CMPSB</nobr></code>, <code><nobr>CMPSW</nobr></code>, <code><nobr>CMPSD</nobr></code>: Compare Strings</a><br>
<a href="nasmdocb.html#section-B.4.28">Section B.4.28: <code><nobr>CMPccSD</nobr></code>: Scalar Double-Precision FP Compare        </a><br>
<a href="nasmdocb.html#section-B.4.29">Section B.4.29: <code><nobr>CMPccSS</nobr></code>: Scalar Single-Precision FP Compare        </a><br>
<a href="nasmdocb.html#section-B.4.30">Section B.4.30: <code><nobr>CMPXCHG</nobr></code>, <code><nobr>CMPXCHG486</nobr></code>: Compare and Exchange</a><br>
<a href="nasmdocb.html#section-B.4.31">Section B.4.31: <code><nobr>CMPXCHG8B</nobr></code>: Compare and Exchange Eight Bytes</a><br>
<a href="nasmdocb.html#section-B.4.32">Section B.4.32: <code><nobr>COMISD</nobr></code>: Scalar Ordered Double-Precision FP Compare and Set EFLAGS</a><br>
<a href="nasmdocb.html#section-B.4.33">Section B.4.33: <code><nobr>COMISS</nobr></code>: Scalar Ordered Single-Precision FP Compare and Set EFLAGS</a><br>
<a href="nasmdocb.html#section-B.4.34">Section B.4.34: <code><nobr>CPUID</nobr></code>: Get CPU Identification Code</a><br>
<a href="nasmdocb.html#section-B.4.35">Section B.4.35: <code><nobr>CVTDQ2PD</nobr></code>: Packed Signed INT32 to Packed Double-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.36">Section B.4.36: <code><nobr>CVTDQ2PS</nobr></code>: Packed Signed INT32 to Packed Single-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.37">Section B.4.37: <code><nobr>CVTPD2DQ</nobr></code>: Packed Double-Precision FP to Packed Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.38">Section B.4.38: <code><nobr>CVTPD2PI</nobr></code>: Packed Double-Precision FP to Packed Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.39">Section B.4.39: <code><nobr>CVTPD2PS</nobr></code>: Packed Double-Precision FP to Packed Single-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.40">Section B.4.40: <code><nobr>CVTPI2PD</nobr></code>: Packed Signed INT32 to Packed Double-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.41">Section B.4.41: <code><nobr>CVTPI2PS</nobr></code>: Packed Signed INT32 to Packed Single-FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.42">Section B.4.42: <code><nobr>CVTPS2DQ</nobr></code>: Packed Single-Precision FP to Packed Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.43">Section B.4.43: <code><nobr>CVTPS2PD</nobr></code>: Packed Single-Precision FP to Packed Double-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.44">Section B.4.44: <code><nobr>CVTPS2PI</nobr></code>: Packed Single-Precision FP to Packed Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.45">Section B.4.45: <code><nobr>CVTSD2SI</nobr></code>: Scalar Double-Precision FP to Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.46">Section B.4.46: <code><nobr>CVTSD2SS</nobr></code>: Scalar Double-Precision FP to Scalar Single-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.47">Section B.4.47: <code><nobr>CVTSI2SD</nobr></code>: Signed INT32 to Scalar Double-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.48">Section B.4.48: <code><nobr>CVTSI2SS</nobr></code>: Signed INT32 to Scalar Single-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.49">Section B.4.49: <code><nobr>CVTSS2SD</nobr></code>: Scalar Single-Precision FP to Scalar Double-Precision FP Conversion</a><br>
<a href="nasmdocb.html#section-B.4.50">Section B.4.50: <code><nobr>CVTSS2SI</nobr></code>: Scalar Single-Precision FP to Signed INT32 Conversion</a><br>
<a href="nasmdocb.html#section-B.4.51">Section B.4.51: <code><nobr>CVTTPD2DQ</nobr></code>: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.52">Section B.4.52: <code><nobr>CVTTPD2PI</nobr></code>: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.53">Section B.4.53: <code><nobr>CVTTPS2DQ</nobr></code>: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.54">Section B.4.54: <code><nobr>CVTTPS2PI</nobr></code>: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.55">Section B.4.55: <code><nobr>CVTTSD2SI</nobr></code>: Scalar Double-Precision FP to Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.56">Section B.4.56: <code><nobr>CVTTSS2SI</nobr></code>: Scalar Single-Precision FP to Signed INT32 Conversion with Truncation</a><br>
<a href="nasmdocb.html#section-B.4.57">Section B.4.57: <code><nobr>DAA</nobr></code>, <code><nobr>DAS</nobr></code>: Decimal Adjustments</a><br>
<a href="nasmdocb.html#section-B.4.58">Section B.4.58: <code><nobr>DEC</nobr></code>: Decrement Integer</a><br>
<a href="nasmdocb.html#section-B.4.59">Section B.4.59: <code><nobr>DIV</nobr></code>: Unsigned Integer Divide</a><br>
<a href="nasmdocb.html#section-B.4.60">Section B.4.60: <code><nobr>DIVPD</nobr></code>: Packed Double-Precision FP Divide</a><br>
<a href="nasmdocb.html#section-B.4.61">Section B.4.61: <code><nobr>DIVPS</nobr></code>: Packed Single-Precision FP Divide</a><br>
<a href="nasmdocb.html#section-B.4.62">Section B.4.62: <code><nobr>DIVSD</nobr></code>: Scalar Double-Precision FP Divide</a><br>
<a href="nasmdocb.html#section-B.4.63">Section B.4.63: <code><nobr>DIVSS</nobr></code>: Scalar Single-Precision FP Divide</a><br>
<a href="nasmdocb.html#section-B.4.64">Section B.4.64: <code><nobr>EMMS</nobr></code>: Empty MMX State</a><br>
<a href="nasmdocb.html#section-B.4.65">Section B.4.65: <code><nobr>ENTER</nobr></code>: Create Stack Frame</a><br>
<a href="nasmdocb.html#section-B.4.66">Section B.4.66: <code><nobr>F2XM1</nobr></code>: Calculate 2**X-1</a><br>
<a href="nasmdocb.html#section-B.4.67">Section B.4.67: <code><nobr>FABS</nobr></code>: Floating-Point Absolute Value</a><br>
<a href="nasmdocb.html#section-B.4.68">Section B.4.68: <code><nobr>FADD</nobr></code>, <code><nobr>FADDP</nobr></code>: Floating-Point Addition</a><br>
<a href="nasmdocb.html#section-B.4.69">Section B.4.69: <code><nobr>FBLD</nobr></code>, <code><nobr>FBSTP</nobr></code>: BCD Floating-Point Load and Store</a><br>
<a href="nasmdocb.html#section-B.4.70">Section B.4.70: <code><nobr>FCHS</nobr></code>: Floating-Point Change Sign</a><br>
<a href="nasmdocb.html#section-B.4.71">Section B.4.71: <code><nobr>FCLEX</nobr></code>, <code><nobr>FNCLEX</nobr></code>: Clear Floating-Point Exceptions</a><br>
<a href="nasmdocb.html#section-B.4.72">Section B.4.72: <code><nobr>FCMOVcc</nobr></code>: Floating-Point Conditional Move</a><br>
<a href="nasmdocb.html#section-B.4.73">Section B.4.73: <code><nobr>FCOM</nobr></code>, <code><nobr>FCOMP</nobr></code>, <code><nobr>FCOMPP</nobr></code>, <code><nobr>FCOMI</nobr></code>, <code><nobr>FCOMIP</nobr></code>: Floating-Point Compare</a><br>
<a href="nasmdocb.html#section-B.4.74">Section B.4.74: <code><nobr>FCOS</nobr></code>: Cosine</a><br>
<a href="nasmdocb.html#section-B.4.75">Section B.4.75: <code><nobr>FDECSTP</nobr></code>: Decrement Floating-Point Stack Pointer</a><br>
<a href="nasmdocb.html#section-B.4.76">Section B.4.76: <code><nobr>FxDISI</nobr></code>, <code><nobr>FxENI</nobr></code>: Disable and Enable Floating-Point Interrupts</a><br>
<a href="nasmdocb.html#section-B.4.77">Section B.4.77: <code><nobr>FDIV</nobr></code>, <code><nobr>FDIVP</nobr></code>, <code><nobr>FDIVR</nobr></code>, <code><nobr>FDIVRP</nobr></code>: Floating-Point Division</a><br>
<a href="nasmdocb.html#section-B.4.78">Section B.4.78: <code><nobr>FEMMS</nobr></code>: Faster Enter/Exit of the MMX or floating-point state</a><br>
<a href="nasmdocb.html#section-B.4.79">Section B.4.79: <code><nobr>FFREE</nobr></code>: Flag Floating-Point Register as Unused</a><br>
<a href="nasmdocb.html#section-B.4.80">Section B.4.80: <code><nobr>FIADD</nobr></code>: Floating-Point/Integer Addition</a><br>
<a href="nasmdocb.html#section-B.4.81">Section B.4.81: <code><nobr>FICOM</nobr></code>, <code><nobr>FICOMP</nobr></code>: Floating-Point/Integer Compare</a><br>
<a href="nasmdocb.html#section-B.4.82">Section B.4.82: <code><nobr>FIDIV</nobr></code>, <code><nobr>FIDIVR</nobr></code>: Floating-Point/Integer Division</a><br>
<a href="nasmdocb.html#section-B.4.83">Section B.4.83: <code><nobr>FILD</nobr></code>, <code><nobr>FIST</nobr></code>, <code><nobr>FISTP</nobr></code>: Floating-Point/Integer Conversion</a><br>
<a href="nasmdocb.html#section-B.4.84">Section B.4.84: <code><nobr>FIMUL</nobr></code>: Floating-Point/Integer Multiplication</a><br>