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<code><nobr>SSE2</nobr></code> and above, it may not be present on all
processors which have <code><nobr>SSE2</nobr></code> support, and it may be
supported on other processors; the <code><nobr>CPUID</nobr></code>
instruction (<a href="#section-B.4.34">section B.4.34</a>) will return a
bit which indicates support for the <code><nobr>CLFLUSH</nobr></code>
instruction.
<h4><a name="section-B.4.22">B.4.22 <code><nobr>CMC</nobr></code>: Complement Carry Flag</a></h4>
<p><pre>
CMC                           ; F5                   [8086]
</pre>
<p><code><nobr>CMC</nobr></code> changes the value of the carry flag: if it
was 0, it sets it to 1, and vice versa.
<h4><a name="section-B.4.23">B.4.23 <code><nobr>CMOVcc</nobr></code>: Conditional Move</a></h4>
<p><pre>
CMOVcc reg16,r/m16            ; o16 0F 40+cc /r      [P6] 
CMOVcc reg32,r/m32            ; o32 0F 40+cc /r      [P6]
</pre>
<p><code><nobr>CMOV</nobr></code> moves its source (second) operand into
its destination (first) operand if the given condition code is satisfied;
otherwise it does nothing.
<p>For a list of condition codes, see <a href="#section-B.2.2">section
B.2.2</a>.
<p>Although the <code><nobr>CMOV</nobr></code> instructions are flagged
<code><nobr>P6</nobr></code> and above, they may not be supported by all
Pentium Pro processors; the <code><nobr>CPUID</nobr></code> instruction
(<a href="#section-B.4.34">section B.4.34</a>) will return a bit which
indicates whether conditional moves are supported.
<h4><a name="section-B.4.24">B.4.24 <code><nobr>CMP</nobr></code>: Compare Integers</a></h4>
<p><pre>
CMP r/m8,reg8                 ; 38 /r                [8086] 
CMP r/m16,reg16               ; o16 39 /r            [8086] 
CMP r/m32,reg32               ; o32 39 /r            [386]
</pre>
<p><pre>
CMP reg8,r/m8                 ; 3A /r                [8086] 
CMP reg16,r/m16               ; o16 3B /r            [8086] 
CMP reg32,r/m32               ; o32 3B /r            [386]
</pre>
<p><pre>
CMP r/m8,imm8                 ; 80 /0 ib             [8086] 
CMP r/m16,imm16               ; o16 81 /0 iw         [8086] 
CMP r/m32,imm32               ; o32 81 /0 id         [386]
</pre>
<p><pre>
CMP r/m16,imm8                ; o16 83 /0 ib         [8086] 
CMP r/m32,imm8                ; o32 83 /0 ib         [386]
</pre>
<p><pre>
CMP AL,imm8                   ; 3C ib                [8086] 
CMP AX,imm16                  ; o16 3D iw            [8086] 
CMP EAX,imm32                 ; o32 3D id            [386]
</pre>
<p><code><nobr>CMP</nobr></code> performs a `mental' subtraction of its
second operand from its first operand, and affects the flags as if the
subtraction had taken place, but does not store the result of the
subtraction anywhere.
<p>In the forms with an 8-bit immediate second operand and a longer first
operand, the second operand is considered to be signed, and is
sign-extended to the length of the first operand. In these cases, the
<code><nobr>BYTE</nobr></code> qualifier is necessary to force NASM to
generate this form of the instruction.
<p>The destination operand can be a register or a memory location. The
source can be a register, memory location or an immediate value of the same
size as the destination.
<h4><a name="section-B.4.25">B.4.25 <code><nobr>CMPccPD</nobr></code>: Packed Double-Precision FP Compare        </a></h4>
<p><pre>
CMPPD xmm1,xmm2/mem128,imm8   ; 66 0F C2 /r ib  [WILLAMETTE,SSE2]
</pre>
<p><pre>
CMPEQPD xmm1,xmm2/mem128      ; 66 0F C2 /r 00  [WILLAMETTE,SSE2] 
CMPLTPD xmm1,xmm2/mem128      ; 66 0F C2 /r 01  [WILLAMETTE,SSE2] 
CMPLEPD xmm1,xmm2/mem128      ; 66 0F C2 /r 02  [WILLAMETTE,SSE2] 
CMPUNORDPD xmm1,xmm2/mem128   ; 66 0F C2 /r 03  [WILLAMETTE,SSE2] 
CMPNEQPD xmm1,xmm2/mem128     ; 66 0F C2 /r 04  [WILLAMETTE,SSE2] 
CMPNLTPD xmm1,xmm2/mem128     ; 66 0F C2 /r 05  [WILLAMETTE,SSE2] 
CMPNLEPD xmm1,xmm2/mem128     ; 66 0F C2 /r 06  [WILLAMETTE,SSE2] 
CMPORDPD xmm1,xmm2/mem128     ; 66 0F C2 /r 07  [WILLAMETTE,SSE2]
</pre>
<p>The <code><nobr>CMPccPD</nobr></code> instructions compare the two
packed double-precision FP values in the source and destination operands,
and returns the result of the comparison in the destination register. The
result of each comparison is a quadword mask of all 1s (comparison true) or
all 0s (comparison false).
<p>The destination is an <code><nobr>XMM</nobr></code> register. The source
can be either an <code><nobr>XMM</nobr></code> register or a 128-bit memory
location.
<p>The third operand is an 8-bit immediate value, of which the low 3 bits
define the type of comparison. For ease of programming, the 8 two-operand
pseudo-instructions are provided, with the third operand already filled in.
The  <code><nobr>Condition Predicates</nobr></code> are:
<p><pre>
EQ     0   Equal 
LT     1   Less-than 
LE     2   Less-than-or-equal 
UNORD  3   Unordered 
NE     4   Not-equal 
NLT    5   Not-less-than 
NLE    6   Not-less-than-or-equal 
ORD    7   Ordered
</pre>
<p>For more details of the comparison predicates, and details of how to
emulate the "greater-than" equivalents, see
<a href="#section-B.2.3">section B.2.3</a>
<h4><a name="section-B.4.26">B.4.26 <code><nobr>CMPccPS</nobr></code>: Packed Single-Precision FP Compare        </a></h4>
<p><pre>
CMPPS xmm1,xmm2/mem128,imm8   ; 0F C2 /r ib     [KATMAI,SSE]
</pre>
<p><pre>
CMPEQPS xmm1,xmm2/mem128      ; 0F C2 /r 00     [KATMAI,SSE] 
CMPLTPS xmm1,xmm2/mem128      ; 0F C2 /r 01     [KATMAI,SSE] 
CMPLEPS xmm1,xmm2/mem128      ; 0F C2 /r 02     [KATMAI,SSE] 
CMPUNORDPS xmm1,xmm2/mem128   ; 0F C2 /r 03     [KATMAI,SSE] 
CMPNEQPS xmm1,xmm2/mem128     ; 0F C2 /r 04     [KATMAI,SSE] 
CMPNLTPS xmm1,xmm2/mem128     ; 0F C2 /r 05     [KATMAI,SSE] 
CMPNLEPS xmm1,xmm2/mem128     ; 0F C2 /r 06     [KATMAI,SSE] 
CMPORDPS xmm1,xmm2/mem128     ; 0F C2 /r 07     [KATMAI,SSE]
</pre>
<p>The <code><nobr>CMPccPS</nobr></code> instructions compare the two
packed single-precision FP values in the source and destination operands,
and returns the result of the comparison in the destination register. The
result of each comparison is a doubleword mask of all 1s (comparison true)
or all 0s (comparison false).
<p>The destination is an <code><nobr>XMM</nobr></code> register. The source
can be either an <code><nobr>XMM</nobr></code> register or a 128-bit memory
location.
<p>The third operand is an 8-bit immediate value, of which the low 3 bits
define the type of comparison. For ease of programming, the 8 two-operand
pseudo-instructions are provided, with the third operand already filled in.
The  <code><nobr>Condition Predicates</nobr></code> are:
<p><pre>
EQ     0   Equal 
LT     1   Less-than 
LE     2   Less-than-or-equal 
UNORD  3   Unordered 
NE     4   Not-equal 
NLT    5   Not-less-than 
NLE    6   Not-less-than-or-equal 
ORD    7   Ordered
</pre>
<p>For more details of the comparison predicates, and details of how to
emulate the "greater-than" equivalents, see
<a href="#section-B.2.3">section B.2.3</a>
<h4><a name="section-B.4.27">B.4.27 <code><nobr>CMPSB</nobr></code>, <code><nobr>CMPSW</nobr></code>, <code><nobr>CMPSD</nobr></code>: Compare Strings</a></h4>
<p><pre>
CMPSB                         ; A6                   [8086] 
CMPSW                         ; o16 A7               [8086] 
CMPSD                         ; o32 A7               [386]
</pre>
<p><code><nobr>CMPSB</nobr></code> compares the byte at
<code><nobr>[DS:SI]</nobr></code> or <code><nobr>[DS:ESI]</nobr></code>
with the byte at <code><nobr>[ES:DI]</nobr></code> or
<code><nobr>[ES:EDI]</nobr></code>, and sets the flags accordingly. It then
increments or decrements (depending on the direction flag: increments if
the flag is clear, decrements if it is set) <code><nobr>SI</nobr></code>
and <code><nobr>DI</nobr></code> (or <code><nobr>ESI</nobr></code> and
<code><nobr>EDI</nobr></code>).
<p>The registers used are <code><nobr>SI</nobr></code> and
<code><nobr>DI</nobr></code> if the address size is 16 bits, and
<code><nobr>ESI</nobr></code> and <code><nobr>EDI</nobr></code> if it is 32
bits. If you need to use an address size not equal to the current
<code><nobr>BITS</nobr></code> setting, you can use an explicit
<code><nobr>a16</nobr></code> or <code><nobr>a32</nobr></code> prefix.
<p>The segment register used to load from <code><nobr>[SI]</nobr></code> or
<code><nobr>[ESI]</nobr></code> can be overridden by using a segment
register name as a prefix (for example,
<code><nobr>ES CMPSB</nobr></code>). The use of
<code><nobr>ES</nobr></code> for the load from
<code><nobr>[DI]</nobr></code> or <code><nobr>[EDI]</nobr></code> cannot be
overridden.
<p><code><nobr>CMPSW</nobr></code> and <code><nobr>CMPSD</nobr></code> work
in the same way, but they compare a word or a doubleword instead of a byte,
and increment or decrement the addressing registers by 2 or 4 instead of 1.
<p>The <code><nobr>REPE</nobr></code> and <code><nobr>REPNE</nobr></code>
prefixes (equivalently, <code><nobr>REPZ</nobr></code> and
<code><nobr>REPNZ</nobr></code>) may be used to repeat the instruction up
to <code><nobr>CX</nobr></code> (or <code><nobr>ECX</nobr></code> - again,
the address size chooses which) times until the first unequal or equal byte
is found.
<h4><a name="section-B.4.28">B.4.28 <code><nobr>CMPccSD</nobr></code>: Scalar Double-Precision FP Compare        </a></h4>
<p><pre>
CMPSD xmm1,xmm2/mem64,imm8    ; F2 0F C2 /r ib  [WILLAMETTE,SSE2]
</pre>
<p><pre>
CMPEQSD xmm1,xmm2/mem64       ; F2 0F C2 /r 00  [WILLAMETTE,SSE2] 
CMPLTSD xmm1,xmm2/mem64       ; F2 0F C2 /r 01  [WILLAMETTE,SSE2] 
CMPLESD xmm1,xmm2/mem64       ; F2 0F C2 /r 02  [WILLAMETTE,SSE2] 
CMPUNORDSD xmm1,xmm2/mem64    ; F2 0F C2 /r 03  [WILLAMETTE,SSE2] 
CMPNEQSD xmm1,xmm2/mem64      ; F2 0F C2 /r 04  [WILLAMETTE,SSE2] 
CMPNLTSD xmm1,xmm2/mem64      ; F2 0F C2 /r 05  [WILLAMETTE,SSE2] 
CMPNLESD xmm1,xmm2/mem64      ; F2 0F C2 /r 06  [WILLAMETTE,SSE2] 
CMPORDSD xmm1,xmm2/mem64      ; F2 0F C2 /r 07  [WILLAMETTE,SSE2]
</pre>
<p>The <code><nobr>CMPccSD</nobr></code> instructions compare the low-order
double-precision FP values in the source and destination operands, and
returns the result of the comparison in the destination register. The
result of each comparison is a quadword mask of all 1s (comparison true) or
all 0s (comparison false).
<p>The destination is an <code><nobr>XMM</nobr></code> register. The source
can be either an <code><nobr>XMM</nobr></code> register or a 128-bit memory
location.
<p>The third operand is an 8-bit immediate value, of which the low 3 bits
define the type of comparison. For ease of programming, the 8 two-operand
pseudo-instructions are provided, with the third operand already filled in.
The  <code><nobr>Condition Predicates</nobr></code> are:
<p><pre>
EQ     0   Equal 
LT     1   Less-than 
LE     2   Less-than-or-equal 
UNORD  3   Unordered 
NE     4   Not-equal 
NLT    5   Not-less-than 
NLE    6   Not-less-than-or-equal 
ORD    7   Ordered
</pre>
<p>For more details of the comparison predicates, and details of how to
emulate the "greater-than" equivalents, see
<a href="#section-B.2.3">section B.2.3</a>
<h4><a name="section-B.4.29">B.4.29 <code><nobr>CMPccSS</nobr></code>: Scalar Single-Precision FP Compare        </a></h4>
<p><pre>
CMPSS xmm1,xmm2/mem32,imm8    ; F3 0F C2 /r ib  [KATMAI,SSE]
</pre>
<p><pre>
CMPEQSS xmm1,xmm2/mem32       ; F3 0F C2 /r 00  [KATMAI,SSE] 
CMPLTSS xmm1,xmm2/mem32       ; F3 0F C2 /r 01  [KATMAI,SSE] 
CMPLESS xmm1,xmm2/mem32       ; F3 0F C2 /r 02  [KATMAI,SSE] 
CMPUNORDSS xmm1,xmm2/mem32    ; F3 0F C2 /r 03  [KATMAI,SSE] 
CMPNEQSS xmm1,xmm2/mem32      ; F3 0F C2 /r 04  [KATMAI,SSE] 
CMPNLTSS xmm1,xmm2/mem32      ; F3 0F C2 /r 05  [KATMAI,SSE] 
CMPNLESS xmm1,xmm2/mem32      ; F3 0F C2 /r 06  [KATMAI,SSE] 
CMPORDSS xmm1,xmm2/mem32      ; F3 0F C2 /r 07  [KATMAI,SSE]
</pre>
<p>The <code><nobr>CMPccSS</nobr></code> instructions compare the low-order
single-precision FP values in the source and destination operands, and
returns the result of the comparison in the destination register. The
result of each comparison is a doubleword mask of all 1s (comparison true)
or all 0s (comparison false).
<p>The destination is an <code><nobr>XMM</nobr></code> register. The source
can be either an <code><nobr>XMM</nobr></code> register or a 128-bit memory
location.
<p>The third operand is an 8-bit immediate value, of which the low 3 bits
define the type of com