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nasm手册 大家可以看看 对要写汇编程序的帮助很大

the various mnemonics are, this table is used to help you work out details
of what is happening.
<p><pre>
Predi-  imm8  Description Relation where:   Emula- Result   QNaN 
 cate  Encod-             A Is 1st Operand  tion   if NaN   Signal 
        ing               B Is 2nd Operand         Operand  Invalid 

EQ     000B   equal       A = B                    False     No 

LT     001B   less-than   A &lt; B                    False     Yes 

LE     010B   less-than-  A &lt;= B                   False     Yes 
               or-equal 

---    ----   greater     A &gt; B             Swap   False     Yes 
              than                          Operands, 
                                            Use LT 

---    ----   greater-    A &gt;= B            Swap   False     Yes 
              than-or-equal                 Operands, 
                                            Use LE 

UNORD  011B   unordered   A, B = Unordered         True      No 

NEQ    100B   not-equal   A != B                   True      No 

NLT    101B   not-less-   NOT(A &lt; B)               True      Yes 
              than 

NLE    110B   not-less-   NOT(A &lt;= B)              True      Yes 
              than-or- 
              equal 

---    ----   not-greater NOT(A &gt; B)        Swap   True      Yes 
              than                          Operands, 
                                            Use NLT 

---    ----   not-greater NOT(A &gt;= B)       Swap   True      Yes 
              than-                         Operands, 
              or-equal                      Use NLE 

ORD    111B   ordered      A , B = Ordered         False     No
</pre>
<p>The unordered relationship is true when at least one of the two values
being compared is a NaN or in an unsupported format.
<p>Note that the comparisons which are listed as not having a predicate or
encoding can only be achieved through software emulation, as described in
the "emulation" column. Note in particular that an instruction such as
<code><nobr>greater-than</nobr></code> is not the same as
<code><nobr>NLE</nobr></code>, as, unlike with the
<code><nobr>CMP</nobr></code> instruction, it has to take into account the
possibility of one operand containing a NaN or an unsupported numeric
format.
<h4><a name="section-B.2.4">B.2.4 Status Flags</a></h4>
<p>The status flags provide some information about the result of the
arithmetic instructions. This information can be used by conditional
instructions (such a <code><nobr>Jcc</nobr></code> and
<code><nobr>CMOVcc</nobr></code>) as well as by some of the other
instructions (such as <code><nobr>ADC</nobr></code> and
<code><nobr>INTO</nobr></code>).
<p>There are 6 status flags:
<p><pre>
CF - Carry flag.
</pre>
<p>Set if an arithmetic operation generates a carry or a borrow out of the
most-significant bit of the result; cleared otherwise. This flag indicates
an overflow condition for unsigned-integer arithmetic. It is also used in
multiple-precision arithmetic.
<p><pre>
PF - Parity flag.
</pre>
<p>Set if the least-significant byte of the result contains an even number
of 1 bits; cleared otherwise.
<p><pre>
AF - Adjust flag.
</pre>
<p>Set if an arithmetic operation generates a carry or a borrow out of bit
3 of the result; cleared otherwise. This flag is used in binary-coded
decimal (BCD) arithmetic.
<p><pre>
ZF - Zero flag.
</pre>
<p>Set if the result is zero; cleared otherwise.
<p><pre>
SF - Sign flag.
</pre>
<p>Set equal to the most-significant bit of the result, which is the sign
bit of a signed integer. (0 indicates a positive value and 1 indicates a
negative value.)
<p><pre>
OF - Overflow flag.
</pre>
<p>Set if the integer result is too large a positive number or too small a
negative number (excluding the sign-bit) to fit in the destination operand;
cleared otherwise. This flag indicates an overflow condition for
signed-integer (two's complement) arithmetic.
<h4><a name="section-B.2.5">B.2.5 Effective Address Encoding: ModR/M and SIB</a></h4>
<p>An effective address is encoded in up to three parts: a ModR/M byte, an
optional SIB byte, and an optional byte, word or doubleword displacement
field.
<p>The ModR/M byte consists of three fields: the
<code><nobr>mod</nobr></code> field, ranging from 0 to 3, in the upper two
bits of the byte, the <code><nobr>r/m</nobr></code> field, ranging from 0
to 7, in the lower three bits, and the spare (register) field in the middle
(bit 3 to bit 5). The spare field is not relevant to the effective address
being encoded, and either contains an extension to the instruction opcode
or the register value of another operand.
<p>The ModR/M system can be used to encode a direct register reference
rather than a memory access. This is always done by setting the
<code><nobr>mod</nobr></code> field to 3 and the
<code><nobr>r/m</nobr></code> field to the register value of the register
in question (it must be a general-purpose register, and the size of the
register must already be implicit in the encoding of the rest of the
instruction). In this case, the SIB byte and displacement field are both
absent.
<p>In 16-bit addressing mode (either <code><nobr>BITS 16</nobr></code> with
no <code><nobr>67</nobr></code> prefix, or
<code><nobr>BITS 32</nobr></code> with a <code><nobr>67</nobr></code>
prefix), the SIB byte is never used. The general rules for
<code><nobr>mod</nobr></code> and <code><nobr>r/m</nobr></code> (there is
an exception, given below) are:
<ul>
<li>The <code><nobr>mod</nobr></code> field gives the length of the
displacement field: 0 means no displacement, 1 means one byte, and 2 means
two bytes.
<li>The <code><nobr>r/m</nobr></code> field encodes the combination of
registers to be added to the displacement to give the accessed address: 0
means <code><nobr>BX+SI</nobr></code>, 1 means
<code><nobr>BX+DI</nobr></code>, 2 means <code><nobr>BP+SI</nobr></code>, 3
means <code><nobr>BP+DI</nobr></code>, 4 means <code><nobr>SI</nobr></code>
only, 5 means <code><nobr>DI</nobr></code> only, 6 means
<code><nobr>BP</nobr></code> only, and 7 means <code><nobr>BX</nobr></code>
only.
</ul>
<p>However, there is a special case:
<ul>
<li>If <code><nobr>mod</nobr></code> is 0 and <code><nobr>r/m</nobr></code>
is 6, the effective address encoded is not <code><nobr>[BP]</nobr></code>
as the above rules would suggest, but instead
<code><nobr>[disp16]</nobr></code>: the displacement field is present and
is two bytes long, and no registers are added to the displacement.
</ul>
<p>Therefore the effective address <code><nobr>[BP]</nobr></code> cannot be
encoded as efficiently as <code><nobr>[BX]</nobr></code>; so if you code
<code><nobr>[BP]</nobr></code> in a program, NASM adds a notional 8-bit
zero displacement, and sets <code><nobr>mod</nobr></code> to 1,
<code><nobr>r/m</nobr></code> to 6, and the one-byte displacement field to
0.
<p>In 32-bit addressing mode (either <code><nobr>BITS 16</nobr></code> with
a <code><nobr>67</nobr></code> prefix, or <code><nobr>BITS 32</nobr></code>
with no <code><nobr>67</nobr></code> prefix) the general rules (again,
there are exceptions) for <code><nobr>mod</nobr></code> and
<code><nobr>r/m</nobr></code> are:
<ul>
<li>The <code><nobr>mod</nobr></code> field gives the length of the
displacement field: 0 means no displacement, 1 means one byte, and 2 means
four bytes.
<li>If only one register is to be added to the displacement, and it is not
<code><nobr>ESP</nobr></code>, the <code><nobr>r/m</nobr></code> field
gives its register value, and the SIB byte is absent. If the
<code><nobr>r/m</nobr></code> field is 4 (which would encode
<code><nobr>ESP</nobr></code>), the SIB byte is present and gives the
combination and scaling of registers to be added to the displacement.
</ul>
<p>If the SIB byte is present, it describes the combination of registers
(an optional base register, and an optional index register scaled by
multiplication by 1, 2, 4 or 8) to be added to the displacement. The SIB
byte is divided into the <code><nobr>scale</nobr></code> field, in the top
two bits, the <code><nobr>index</nobr></code> field in the next three, and
the <code><nobr>base</nobr></code> field in the bottom three. The general
rules are:
<ul>
<li>The <code><nobr>base</nobr></code> field encodes the register value of
the base register.
<li>The <code><nobr>index</nobr></code> field encodes the register value of
the index register, unless it is 4, in which case no index register is used
(so <code><nobr>ESP</nobr></code> cannot be used as an index register).
<li>The <code><nobr>scale</nobr></code> field encodes the multiplier by
which the index register is scaled before adding it to the base and
displacement: 0 encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3
encodes 8.
</ul>
<p>The exceptions to the 32-bit encoding rules are:
<ul>
<li>If <code><nobr>mod</nobr></code> is 0 and <code><nobr>r/m</nobr></code>
is 5, the effective address encoded is not <code><nobr>[EBP]</nobr></code>
as the above rules would suggest, but instead
<code><nobr>[disp32]</nobr></code>: the displacement field is present and
is four bytes long, and no registers are added to the displacement.
<li>If <code><nobr>mod</nobr></code> is 0, <code><nobr>r/m</nobr></code> is
4 (meaning the SIB byte is present) and <code><nobr>base</nobr></code> is
4, the effective address encoded is not
<code><nobr>[EBP+index]</nobr></code> as the above rules would suggest, but
instead <code><nobr>[disp32+index]</nobr></code>: the displacement field is
present and is four bytes long, and there is no base register (but the
index register is still processed in the normal way).
</ul>
<h3><a name="section-B.3">B.3 Key to Instruction Flags</a></h3>
<p>Given along with each instruction in this appendix is a set of flags,
denoting the type of the instruction. The types are as follows:
<ul>
<li><code><nobr>8086</nobr></code>, <code><nobr>186</nobr></code>,
<code><nobr>286</nobr></code>, <code><nobr>386</nobr></code>,
<code><nobr>486</nobr></code>, <code><nobr>PENT</nobr></code> and
<code><nobr>P6</nobr></code> denote the lowest processor type that supports
the instruction. Most instructions run on all processors above the given
type; those that do not are documented. The Pentium II contains no
additional instructions beyond the P6 (Pentium Pro); from the point of view
of its instruction set, it can be thought of as a P6 with MMX capability.
<li><code><nobr>3DNOW</nobr></code> indicates that the instruction is a
3DNow! one, and will run on the AMD K6-2 and later processors. ATHLON
extensions to the 3DNow! instruction set are documented as such.
<li><code><nobr>CYRIX</nobr></code> indicates that the instruction is
specific to Cyrix processors, for example the extra MMX instructions in the
Cyrix extended MMX instruction set.
<li><code><nobr>FPU</nobr></code> indicates that the instruction is a
floating-point one, and will only run on machines with a coprocessor
(automatically including 486DX, Pentium and above).
<li><code><nobr>KATMAI</nobr></code> indicates that the instruction was
introduced as part of the Katmai New Instruction set. These instructions
are available on the Pentium III and later processors. Those which are not
specifically SSE instructions are also available on the AMD Athlon.
<li><code><nobr>MMX</nobr></code> indicates that the instruction is an MMX
one, and will run on MMX-capable Pentium processors and the Pentium II.
<li><code><nobr>PRIV</nobr></code> indicates that the instruction is a
protected-mode management instruction. Many of these may only be used in
protected mode, or only at privilege level zero.
<li><code><nobr>SSE</nobr></code> and <code><nobr>SSE2</nobr></code>
indicate that the instruction is a Streaming SIMD Extension instruction.
These instructions operate on multiple values in a single operation. SSE
was introduced with the Pentium III and SSE2 was introduced with the
Pentium 4.
<li><code><nobr>UNDOC</nobr></code> indicates that the instruction is an
undocumented one, and not part of the official Intel Architecture; it may
or may not be supported on any given machine.
<li><code><nobr>WILLAMETTE</nobr></code> indicates that the instruction was
introduced as part of the new instruction set in the Pentium 4 and Intel
Xeon processors. These instructions are also known as SSE2 instructions.
</ul>
<h3><a name="section-B.4">B.4 x86 Instruction Set</a></h3>
<h4><a name="section-B.4.1">B.4.1 <code><nobr>AAA</nobr></code>, <code><nobr>AAS</nobr></code>, <code><nobr>AAM</nobr></code>, <code><nobr>AAD</nobr></code>: ASCII Adjustments</a></h4>
<p><pre>
AAA                           ; 37                   [8086]
</pre>