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<html><head><title>NASM Manual</title></head><body><h1 align=center>The Netwide Assembler: NASM</h1><p align=center><a href="nasmdoca.html">Previous Chapter</a> |<a href="nasmdoc0.html">Contents</a> |<a href="nasmdoci.html">Index</a><h2><a name="appendix-B">Appendix B: x86 Instruction Reference</a></h2><p>This appendix provides a complete list of the machine instructions whichNASM will assemble, and a short description of the function of each one.<p>It is not intended to be exhaustive documentation on the fine details ofthe instructions' function, such as which exceptions they can trigger: forsuch documentation, you should go to Intel's Web site,<a href="http://developer.intel.com/design/Pentium4/manuals/"><code><nobr>http://developer.intel.com/design/Pentium4/manuals/</nobr></code></a>.<p>Instead, this appendix is intended primarily to provide documentation onthe way the instructions may be used within NASM. For example, looking up<code><nobr>LOOP</nobr></code> will tell you that NASM allows<code><nobr>CX</nobr></code> or <code><nobr>ECX</nobr></code> to bespecified as an optional second argument to the<code><nobr>LOOP</nobr></code> instruction, to enforce which of the twopossible counter registers should be used if the default is not the onedesired.<p>The instructions are not quite listed in alphabetical order, sincegroups of instructions with similar functions are lumped together in thesame entry. Most of them don't move very far from their alphabetic positionbecause of this.<h3><a name="section-B.1">B.1 Key to Operand Specifications</a></h3><p>The instruction descriptions in this appendix specify their operandsusing the following notation:<ul><li>Registers: <code><nobr>reg8</nobr></code> denotes an 8-bit generalpurpose register, <code><nobr>reg16</nobr></code> denotes a 16-bit generalpurpose register, and <code><nobr>reg32</nobr></code> a 32-bit one.<code><nobr>fpureg</nobr></code> denotes one of the eight FPU stackregisters, <code><nobr>mmxreg</nobr></code> denotes one of the eight 64-bitMMX registers, and <code><nobr>segreg</nobr></code> denotes a segmentregister. In addition, some registers (such as<code><nobr>AL</nobr></code>, <code><nobr>DX</nobr></code> or<code><nobr>ECX</nobr></code>) may be specified explicitly.<li>Immediate operands: <code><nobr>imm</nobr></code> denotes a genericimmediate operand. <code><nobr>imm8</nobr></code>,<code><nobr>imm16</nobr></code> and <code><nobr>imm32</nobr></code> areused when the operand is intended to be a specific size. For some of theseinstructions, NASM needs an explicit specifier: for example,<code><nobr>ADD ESP,16</nobr></code> could be interpreted as either<code><nobr>ADD r/m32,imm32</nobr></code> or<code><nobr>ADD r/m32,imm8</nobr></code>. NASM chooses the former bydefault, and so you must specify <code><nobr>ADD ESP,BYTE 16</nobr></code>for the latter.<li>Memory references: <code><nobr>mem</nobr></code> denotes a genericmemory reference; <code><nobr>mem8</nobr></code>,<code><nobr>mem16</nobr></code>, <code><nobr>mem32</nobr></code>,<code><nobr>mem64</nobr></code> and <code><nobr>mem80</nobr></code> areused when the operand needs to be a specific size. Again, a specifier isneeded in some cases: <code><nobr>DEC [address]</nobr></code> is ambiguousand will be rejected by NASM. You must specify<code><nobr>DEC BYTE [address]</nobr></code>,<code><nobr>DEC WORD [address]</nobr></code> or<code><nobr>DEC DWORD [address]</nobr></code> instead.<li>Restricted memory references: one form of the<code><nobr>MOV</nobr></code> instruction allows a memory address to bespecified <em>without</em> allowing the normal range of registercombinations and effective address processing. This is denoted by<code><nobr>memoffs8</nobr></code>, <code><nobr>memoffs16</nobr></code> and<code><nobr>memoffs32</nobr></code>.<li>Register or memory choices: many instructions can accept either aregister <em>or</em> a memory reference as an operand.<code><nobr>r/m8</nobr></code> is a shorthand for<code><nobr>reg8/mem8</nobr></code>; similarly<code><nobr>r/m16</nobr></code> and <code><nobr>r/m32</nobr></code>.<code><nobr>r/m64</nobr></code> is MMX-related, and is a shorthand for<code><nobr>mmxreg/mem64</nobr></code>.</ul><h3><a name="section-B.2">B.2 Key to Opcode Descriptions</a></h3><p>This appendix also provides the opcodes which NASM will generate foreach form of each instruction. The opcodes are listed in the following way:<ul><li>A hex number, such as <code><nobr>3F</nobr></code>, indicates a fixedbyte containing that number.<li>A hex number followed by <code><nobr>+r</nobr></code>, such as<code><nobr>C8+r</nobr></code>, indicates that one of the operands to theinstruction is a register, and the `register value' of that register shouldbe added to the hex number to produce the generated byte. For example, EDXhas register value 2, so the code <code><nobr>C8+r</nobr></code>, when theregister operand is EDX, generates the hex byte<code><nobr>CA</nobr></code>. Register values for specific registers aregiven in <a href="#section-B.2.1">section B.2.1</a>.<li>A hex number followed by <code><nobr>+cc</nobr></code>, such as<code><nobr>40+cc</nobr></code>, indicates that the instruction name has acondition code suffix, and the numeric representation of the condition codeshould be added to the hex number to produce the generated byte. Forexample, the code <code><nobr>40+cc</nobr></code>, when the instructioncontains the <code><nobr>NE</nobr></code> condition, generates the hex byte<code><nobr>45</nobr></code>. Condition codes and their numericrepresentations are given in <a href="#section-B.2.2">section B.2.2</a>.<li>A slash followed by a digit, such as <code><nobr>/2</nobr></code>,indicates that one of the operands to the instruction is a memory addressor register (denoted <code><nobr>mem</nobr></code> or<code><nobr>r/m</nobr></code>, with an optional size). This is to beencoded as an effective address, with a ModR/M byte, an optional SIB byte,and an optional displacement, and the spare (register) field of the ModR/Mbyte should be the digit given (which will be from 0 to 7, so it fits inthree bits). The encoding of effective addresses is given in<a href="#section-B.2.5">section B.2.5</a>.<li>The code <code><nobr>/r</nobr></code> combines the above two: itindicates that one of the operands is a memory address or<code><nobr>r/m</nobr></code>, and another is a register, and that aneffective address should be generated with the spare (register) field inthe ModR/M byte being equal to the `register value' of the registeroperand. The encoding of effective addresses is given in<a href="#section-B.2.5">section B.2.5</a>; register values are given in<a href="#section-B.2.1">section B.2.1</a>.<li>The codes <code><nobr>ib</nobr></code>, <code><nobr>iw</nobr></code>and <code><nobr>id</nobr></code> indicate that one of the operands to theinstruction is an immediate value, and that this is to be encoded as abyte, little-endian word or little-endian doubleword respectively.<li>The codes <code><nobr>rb</nobr></code>, <code><nobr>rw</nobr></code>and <code><nobr>rd</nobr></code> indicate that one of the operands to theinstruction is an immediate value, and that the <em>difference</em> betweenthis value and the address of the end of the instruction is to be encodedas a byte, word or doubleword respectively. Where the form<code><nobr>rw/rd</nobr></code> appears, it indicates that either<code><nobr>rw</nobr></code> or <code><nobr>rd</nobr></code> should be usedaccording to whether assembly is being performed in<code><nobr>BITS 16</nobr></code> or <code><nobr>BITS 32</nobr></code>state respectively.<li>The codes <code><nobr>ow</nobr></code> and <code><nobr>od</nobr></code>indicate that one of the operands to the instruction is a reference to thecontents of a memory address specified as an immediate value: this encodingis used in some forms of the <code><nobr>MOV</nobr></code> instruction inplace of the standard effective-address mechanism. The displacement isencoded as a word or doubleword. Again, <code><nobr>ow/od</nobr></code>denotes that <code><nobr>ow</nobr></code> or <code><nobr>od</nobr></code>should be chosen according to the <code><nobr>BITS</nobr></code> setting.<li>The codes <code><nobr>o16</nobr></code> and<code><nobr>o32</nobr></code> indicate that the given form of theinstruction should be assembled with operand size 16 or 32 bits. In otherwords, <code><nobr>o16</nobr></code> indicates a<code><nobr>66</nobr></code> prefix in <code><nobr>BITS 32</nobr></code>state, but generates no code in <code><nobr>BITS 16</nobr></code> state;and <code><nobr>o32</nobr></code> indicates a <code><nobr>66</nobr></code>prefix in <code><nobr>BITS 16</nobr></code> state but generates nothing in<code><nobr>BITS 32</nobr></code>.<li>The codes <code><nobr>a16</nobr></code> and<code><nobr>a32</nobr></code>, similarly to <code><nobr>o16</nobr></code>and <code><nobr>o32</nobr></code>, indicate the address size of the givenform of the instruction. Where this does not match the<code><nobr>BITS</nobr></code> setting, a <code><nobr>67</nobr></code>prefix is required.</ul><h4><a name="section-B.2.1">B.2.1 Register Values</a></h4><p>Where an instruction requires a register value, it is already implicitin the encoding of the rest of the instruction what type of register isintended: an 8-bit general-purpose register, a segment register, a debugregister, an MMX register, or whatever. Therefore there is no problem withregisters of different types sharing an encoding value.<p>The encodings for the various classes of register are:<ul><li>8-bit general registers: <code><nobr>AL</nobr></code> is 0,<code><nobr>CL</nobr></code> is 1, <code><nobr>DL</nobr></code> is 2,<code><nobr>BL</nobr></code> is 3, <code><nobr>AH</nobr></code> is 4,<code><nobr>CH</nobr></code> is 5, <code><nobr>DH</nobr></code> is 6, and<code><nobr>BH</nobr></code> is 7.<li>16-bit general registers: <code><nobr>AX</nobr></code> is 0,<code><nobr>CX</nobr></code> is 1, <code><nobr>DX</nobr></code> is 2,<code><nobr>BX</nobr></code> is 3, <code><nobr>SP</nobr></code> is 4,<code><nobr>BP</nobr></code> is 5, <code><nobr>SI</nobr></code> is 6, and<code><nobr>DI</nobr></code> is 7.<li>32-bit general registers: <code><nobr>EAX</nobr></code> is 0,<code><nobr>ECX</nobr></code> is 1, <code><nobr>EDX</nobr></code> is 2,<code><nobr>EBX</nobr></code> is 3, <code><nobr>ESP</nobr></code> is 4,<code><nobr>EBP</nobr></code> is 5, <code><nobr>ESI</nobr></code> is 6, and<code><nobr>EDI</nobr></code> is 7.<li>Segment registers: <code><nobr>ES</nobr></code> is 0,<code><nobr>CS</nobr></code> is 1, <code><nobr>SS</nobr></code> is 2,<code><nobr>DS</nobr></code> is 3, <code><nobr>FS</nobr></code> is 4, and<code><nobr>GS</nobr></code> is 5.<li>Floating-point registers: <code><nobr>ST0</nobr></code> is 0,<code><nobr>ST1</nobr></code> is 1, <code><nobr>ST2</nobr></code> is 2,<code><nobr>ST3</nobr></code> is 3, <code><nobr>ST4</nobr></code> is 4,<code><nobr>ST5</nobr></code> is 5, <code><nobr>ST6</nobr></code> is 6, and<code><nobr>ST7</nobr></code> is 7.<li>64-bit MMX registers: <code><nobr>MM0</nobr></code> is 0,<code><nobr>MM1</nobr></code> is 1, <code><nobr>MM2</nobr></code> is 2,<code><nobr>MM3</nobr></code> is 3, <code><nobr>MM4</nobr></code> is 4,<code><nobr>MM5</nobr></code> is 5, <code><nobr>MM6</nobr></code> is 6, and<code><nobr>MM7</nobr></code> is 7.<li>Control registers: <code><nobr>CR0</nobr></code> is 0,<code><nobr>CR2</nobr></code> is 2, <code><nobr>CR3</nobr></code> is 3, and<code><nobr>CR4</nobr></code> is 4.<li>Debug registers: <code><nobr>DR0</nobr></code> is 0,<code><nobr>DR1</nobr></code> is 1, <code><nobr>DR2</nobr></code> is 2,<code><nobr>DR3</nobr></code> is 3, <code><nobr>DR6</nobr></code> is 6, and<code><nobr>DR7</nobr></code> is 7.<li>Test registers: <code><nobr>TR3</nobr></code> is 3,<code><nobr>TR4</nobr></code> is 4, <code><nobr>TR5</nobr></code> is 5,<code><nobr>TR6</nobr></code> is 6, and <code><nobr>TR7</nobr></code> is 7.</ul><p>(Note that wherever a register name contains a number, that number isalso the register value for that register.)<h4><a name="section-B.2.2">B.2.2 Condition Codes</a></h4><p>The available condition codes are given here, along with their numericrepresentations as part of opcodes. Many of these condition codes havesynonyms, so several will be listed at a time.<p>In the following descriptions, the word `either', when applied to twopossible trigger conditions, is used to mean `either or both'. If `eitherbut not both' is meant, the phrase `exactly one of' is used.<ul><li><code><nobr>O</nobr></code> is 0 (trigger if the overflow flag is set);<code><nobr>NO</nobr></code> is 1.<li><code><nobr>B</nobr></code>, <code><nobr>C</nobr></code> and<code><nobr>NAE</nobr></code> are 2 (trigger if the carry flag is set);<code><nobr>AE</nobr></code>, <code><nobr>NB</nobr></code> and<code><nobr>NC</nobr></code> are 3.<li><code><nobr>E</nobr></code> and <code><nobr>Z</nobr></code> are 4(trigger if the zero flag is set); <code><nobr>NE</nobr></code> and<code><nobr>NZ</nobr></code> are 5.<li><code><nobr>BE</nobr></code> and <code><nobr>NA</nobr></code> are 6(trigger if either of the carry or zero flags is set);<code><nobr>A</nobr></code> and <code><nobr>NBE</nobr></code> are 7.<li><code><nobr>S</nobr></code> is 8 (trigger if the sign flag is set);<code><nobr>NS</nobr></code> is 9.<li><code><nobr>P</nobr></code> and <code><nobr>PE</nobr></code> are 10(trigger if the parity flag is set); <code><nobr>NP</nobr></code> and<code><nobr>PO</nobr></code> are 11.<li><code><nobr>L</nobr></code> and <code><nobr>NGE</nobr></code> are 12(trigger if exactly one of the sign and overflow flags is set);<code><nobr>GE</nobr></code> and <code><nobr>NL</nobr></code> are 13.<li><code><nobr>LE</nobr></code> and <code><nobr>NG</nobr></code> are 14(trigger if either the zero flag is set, or exactly one of the sign andoverflow flags is set); <code><nobr>G</nobr></code> and<code><nobr>NLE</nobr></code> are 15.</ul><p>Note that in all cases, the sense of a condition code may be reversed bychanging the low bit of the numeric representation.<p>For details of when an instruction sets each of the status flags, seethe individual instruction, plus the Status Flags reference in<a href="#section-B.2.4">section B.2.4</a><h4><a name="section-B.2.3">B.2.3 SSE Condition Predicates</a></h4><p>The condition predicates for SSE comparison instructions are the codesused as part of the opcode, to determine what form of comparison is beingcarried out. In each case, the imm8 value is the final byte of the opcodeencoding, and the predicate is the code used as part of the mnemonic forthe instruction (equivalent to the "cc" in an integer instruction that useda condition code). The instructions that use this will give details of what⌨️ 快捷键说明
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