head.s

此dma 也是SBC开发板的

@ Memory Controller 
#define MEM_CTL_BASE	0x48000000

@ Clock register
#define CLK_CTL_BASE	0x4c000000
@ Offset 
#define oLOCKTIME	0x00	@ R/W, PLL lock time count register 
#define oMPLLCON	0x04	@ R/W, MPLL configuration register 
#define oUPLLCON	0x08	@ R/W, UPLL configuration register 
#define oCLKCON		0x0C	@ R/W, Clock generator control reg.
#define oCLKSLOW	0x10	@ R/W, Slow clock control register 
#define oCLKDIVN	0x14	@ R/W, Clock divider control 

@ 200.00 MHz 
#define MDIV_200	0x5c
#define PDIV_200	0x4
#define SDIV_200	0x0
#define mpll_200mhz	((MDIV_200 << 12) | (PDIV_200 << 4) | (SDIV_200)) 

@ Uart register
#define GPHCON	0x56000070
#define GPHDAT	0x56000074
#define GPHUP   0x56000078
#define UART_CTL_BASE	0x50000000
#define	reg(i)	(UART_CTL_BASE + i)
#define	Ulcon0	reg(0x00)
#define Ucon0	reg(0x04)
#define	Utrstat0	reg(0x10)
#define Utxh0	reg(0x20)
#define	Ubrdiv0	reg(0x28)

@ NAND Flash Controller 
#define NAND_CTL_BASE	0x4E000000
#define oNFCONF		0x00
#define oNFCMD		0x04
#define oNFADDR		0x08
#define oNFDATA		0x0c
#define oNFSTAT		0x10
#define oNFECC		0x14

@DMA register
#define DISRC0	0x4b000000	@source address register
#define DISRCC0	0x4b000004	@source control register
#define DIDST0	0x4b000008	@destination address reg
#define DIDSTC0	0x4b00000c	@destination control reg
#define DCON0	0x4b000010	@cotrol register
#define DSTAT0	0x4b000014	@staut register
#define DCSRC0	0x4b000018	@current source addr reg
#define DCDST0	0x4b00001c	@current destin addr reg
#define DMASKTRIG0	0x4b000020	@trriger mask register

.global _start
_start:

	@ disable watch dog timer
	mov	r1, #0x53000000
	mov	r2, #0x0
	str	r2, [r1]

	bl	InitMem
	bl	InitClk
	bl	InitUart
	bl	CopyToSdram
	b	Main

	@ initialize the static memory 
InitMem:
	@ set memory control registers
	mov	r1, #MEM_CTL_BASE
	adrl	r2, mem_cfg_val
	add	r3, r1, #52
1:	ldr	r4, [r2], #4
	str	r4, [r1], #4
	cmp	r1, r3
	bne	1b
	mov	pc, lr

	@ set system clocks
InitClk:
	mov	r1, #CLK_CTL_BASE
	mvn	r2, #0xff000000
	str	r2, [r1, #0x00]			@ set LOCKTIME

	@ 1:2:4
	mov	r1, #CLK_CTL_BASE
	mov	r2, #0x3
	str	r2, [r1,  #0x14]		@set CLKDIVN

	mrc	p15, 0, r1, c1, c0, 0		@ read ctrl register 
	orr	r1, r1, #0xc0000000		@ Asynchronous  
	mcr	p15, 0, r1, c1, c0, 0		@ write ctrl register

	@ now, CPU clock is 200 Mhz
	mov	r1, #CLK_CTL_BASE
	ldr	r2, =mpll_200mhz
	str	r2, [r1, #0x04]			@set MPLLCON
	mov	pc, lr

InitUart:
	@ set GPHCON
	ldr	r0, =GPHCON
	ldr	r1, [r0]
	ldr	r2, =0xffff
	bic	r1, r1, r2
	ldr	r2, =0xaaaa
	orr	r1, r1, r2
	str	r1, [r0]

	@set GPHUP	
	ldr	r0, =GPHUP
	ldr	r1, [r0]
	ldr	r2 , =0x7ff
	bic	r1, r1, r2
	str	r1, [r0]

	@set ULCON0
	ldr	r0, =Ulcon0
	ldr	r1, [r1]
	bic	r1, r1, #0xff
	orr	r1, r1, #0x03
	str	r1, [r0]

	@set UCON0
	ldr	r0, =Ucon0
	ldr	r1, [r0]
	bic	r1, r1, #0xff
	orr	r1, r1, #0x5
	str	r1, [r0] 

	@set UBRDIV0
	ldr	r0, =Ubrdiv0
	ldr	r1, [r0]
	ldr	r2, =0xffff
	bic	r1, r1, r2
	orr	r1, r1, #0x1a
	str 	r1, [r0]
	
	mov	pc, lr

CopyToSdram:
	@initial NAND control NAND chip
	mov	r1, #NAND_CTL_BASE
	ldr	r2, =0xf030			@nand flash control enable
	str	r2, [r1, #oNFCONF]
	@{{ reset 
	mov	r2, #0xff
	strb	r2, [r1, #oNFCMD]
2:	
	ldr	r2, [r1, #oNFSTAT]		@staut inquiry
	tst	r2, #0x1
	beq	2b
	@}}reset end
	@{{read
	ldr	r5, =0x30000100			@destination start address
	mov	r6, #0				@page account
3:	
	mov 	r2, #0
	strb	r2, [r1, #oNFCMD]
	strb 	r2, [r1, #oNFADDR]		@row address(in feild offset address)
	strb	r6, [r1, #oNFADDR]		@page address & block address
	strb 	r2, [r1, #oNFADDR]		@block address 0
	strb 	r2, [r1, #oNFADDR]		@block address 0
4:	
	ldr	r2, [r1, #oNFSTAT]		@staut inquiry
	tst	r2, #0x1
	beq	4b
	mov	r7, #512			@a page bytes 
5:	
	ldr	r2, [r1, #oNFDATA]
	strb	r2, [r5],#1
	subs	r7, r7,	#1
	bne	5b
	add	r6, r6,	#1
	cmp	r6, #16				@copy 16 pages 8K
	blt	3b
	@}}read end
	@NAND chip disable
	ldr	r2, [r1, #oNFCONF]
	orr	r2, r2, #0x800			@off
	str	r2, [r1, #oNFCONF]
	mov	pc, lr			

@ Data Area
@
@ Memory configuration values
.align 4
mem_cfg_val:
	.long	0x22111110 @vBWSCON
	.long	0x00000700 @vBANKCON0
	.long	0x00000700 @vBANKCON1
	.long	0x00000700 @vBANKCON2
	.long	0x00000700 @vBANKCON3
	.long	0x00000700 @vBANKCON4
	.long	0x00000700 @vBANKCON5
	.long	0x00018005 @vBANKCON6
	.long	0x00018005 @vBANKCON7
	.long	0x008e0459 @vREFRESH
	.long	0xb2		  @vBANKSIZE
	.long	0x30		  @vMRSRB6
	.long	0x30		  @vMRSRB7