chipio.vhd

this is a vhdl version of MiniUART implementation

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--
-- RS232 Example Project
-- Doug Hodson, May 2003
-- www.RetroMicro.com
--
entity chipIO is
   
   port(
      pin_sysclk  : in std_logic;                      -- master clock from external clock source

      -- misc buttons and leds
      pin_pushbtn : in std_logic;                      -- push button on XSA board
      pin_led     : out std_logic_vector(6 downto 0);  -- 7-segment LED
      
      -- Flash RAM connections
      pin_flash_ce_n  : out std_logic;  -- chip-enable
      
      -- parallel port connections
      --parport_d: in std_logic_vector(7 downto 0);
      pin_parport_d : in std_logic_vector(4 downto 0);
      pin_parport_s : out std_logic_vector(6 downto 3);
      
      -- vga port connections
      pin_vga_red     : out std_logic_vector(1 downto 0);
      pin_vga_green   : out std_logic_vector(1 downto 0);
      pin_vga_blue    : out std_logic_vector(1 downto 0);
      pin_vga_hsync_n : out std_logic;
      pin_vga_vsync_n : out std_logic;

      -- SDRAM pin connections
      pin_sdram_clkfb : in std_logic;                   -- feedback clock with PCB delays
      pin_sdram_clk   : out std_logic;                  -- clock to RAM
      pin_sdram_cke   : out std_logic;                  -- clock-enable
      pin_sdram_cs_n  : out std_logic;                  -- chip-select
      pin_sdram_ras_n : out std_logic;                  -- RAS
      pin_sdram_cas_n : out std_logic;                  -- CAS
      pin_sdram_we_n  : out std_logic;                  -- write-enable
      pin_sdram_ba    : out unsigned( 1 downto 0);      -- bank-address
      pin_sdram_addr  : out unsigned(11 downto 0);      -- address bus
      pin_sdram_data  : inout unsigned(16-1 downto 0);  -- data bus
      pin_sdram_dqmh  : out std_logic;                  -- DQMH
      pin_sdram_dqml  : out std_logic;                  -- DQML
      
      -- RS232 port connections
      pin_rs232_rd    : in std_logic;                   -- receive data
      pin_rs232_td    : out std_logic;                  -- transmit data
      pin_rs232_cts   : in std_logic;                   -- clear to send
      pin_rs232_rts   : out std_logic;                  -- request to send

      -- XStend-2 SRAM connections
      pin_sram_ce_n   : out std_logic                   -- chip enable
   );
   
end chipIO;

architecture arch of chipIO is

	constant YES:	std_logic := '1';
	constant NO:	std_logic := '0';
	constant HI:	std_logic := '1';
	constant LO:	std_logic := '0';

   signal sysClk   : std_logic;  -- system clock
   signal sysReset : std_logic;  -- system reset
   
   -- uart component
   component uart
      generic(BRDIVISOR: INTEGER range 0 to 65535 := 130); -- baudrate divisor
      port(
      -- Wishbone signals
      WB_CLK_I : in  std_logic;  -- clock
      WB_RST_I : in  std_logic;  -- Reset input
      WB_ADR_I : in  std_logic_vector(1 downto 0); -- Adress bus          
      WB_DAT_I : in  std_logic_vector(7 downto 0); -- DataIn Bus
      WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
      WB_WE_I  : in  std_logic;  -- Write Enable
      WB_STB_I : in  std_logic;  -- Strobe
      WB_ACK_O : out std_logic;  -- Acknowledge
      -- process signals     
      IntTx_O  : out std_logic;  -- Transmit interrupt: indicate waiting for Byte
      IntRx_O  : out std_logic;  -- Receive interrupt: indicate Byte received
      BR_Clk_I : in  std_logic;  -- Clock used for Transmit/Receive
      TxD_PAD_O: out std_logic;  -- Tx RS232 Line
      RxD_PAD_I: in  std_logic);  -- Rx RS232 Line     
   end component;

   -- uart signals
   signal uart_WB_CLK_I : std_logic;
   signal uart_WB_RST_I : std_logic;
   signal uart_WB_ADR_I : std_logic_vector(1 downto 0);          
   signal uart_WB_DAT_I : std_logic_vector(7 downto 0);
   signal uart_WB_DAT_O : std_logic_vector(7 downto 0);
   signal uart_WB_WE_I  : std_logic;
   signal uart_WB_STB_I : std_logic;
   signal uart_WB_ACK_O : std_logic;
   signal uart_IntTx_O  : std_logic;
   signal uart_IntRx_O  : std_logic;
   signal uart_BR_Clk_I : std_logic;
   signal uart_TxD_PAD_O: std_logic;
   signal uart_RxD_PAD_I: std_logic;     
   
   signal charBuf : std_logic_vector(7 downto 0);
   signal charAvail : std_logic;
begin

   -- disable flash and sram
   pin_flash_ce_n <= '1';
   pin_sram_ce_n <= '1';

   -- define system clock and reset
   sysClk   <= pin_sysclk;
   sysReset <= not pin_pushbtn;

   -- setup uart signals
   uart_WB_ADR_I  <= "00";           -- receive/transmit buffer

	-- main code to echo keyboard input
   process(uart_IntRx_O, uart_IntTx_O)
   begin
  		if( uart_IntRx_O=HI ) then
   		charBuf        <= uart_WB_DAT_O;     -- store char received in buffer
   		charAvail      <= YES;
   		uart_WB_WE_I   <= LO;                -- read from uart
			uart_WB_STB_I  <= HI;                -- strobe uart
		elsif( uart_IntTx_O=HI ) then
			if( charAvail=YES ) then
   			uart_WB_DAT_I  <= charBuf;        -- store buffer in uart
   			charAvail      <= NO;
   			uart_WB_WE_I   <= HI;             -- write to uart
 				uart_WB_STB_I  <= HI;             -- strobe uart
 			end if;
		else
			charBuf <= "00000000";               -- clear buffer			
			uart_WB_STB_I <= LO;
      end if;
   end process;

   --
   -- CREATE COMPONENTS
   --
   
   -- serial rs232 driver component
   -- 260 -> 9600 baud for clock at 10MHz
   sysuart: uart
   generic map(BRDIVISOR => 260)
   port map(
      -- Wishbone signals
      WB_CLK_I  => uart_WB_CLK_I,
      WB_RST_I  => uart_WB_RST_I,
      WB_ADR_I  => uart_WB_ADR_I,          
      WB_DAT_I  => uart_WB_DAT_I,
      WB_DAT_O  => uart_WB_DAT_O,
      WB_WE_I   => uart_WB_WE_I,
      WB_STB_I  => uart_WB_STB_I,
      WB_ACK_O  => uart_WB_ACK_O,
      -- process signals     
      IntTx_O   => uart_IntTx_O,
      IntRx_O   => uart_IntRx_O,
      BR_Clk_I  => uart_BR_Clk_I,
      TxD_PAD_O => uart_TxD_PAD_O,
      RxD_PAD_I => uart_RxD_PAD_I
      );

   -- uart port connections/conversions
   uart_WB_CLK_I  <= sysClk;         -- wishbone clock
   uart_WB_RST_I  <= sysReset;       -- reset
   uart_BR_Clk_I  <= sysClk;         -- baudrate clock
   pin_rs232_td   <= uart_TxD_PAD_O; -- transmit
   uart_RxD_PAD_I <= pin_rs232_rd;   -- receive

end arch;