📄 spitest.lst
字号:
00000042 2180 MOV R1,#0x80
00000044 4800 LDR R0,=0xE0028004
00000046 6001 STR R1,[R0,#0x0]
47: if ( SPIRDData[0] & (RDSR_WEN|RDSR_RDY) != RDSR_WEN )
00000048 4800 LDR R0,=SPIRDData ; SPIRDData
0000004A 7800 LDRB R0,[R0,#0x0] ; SPIRDData
0000004C 2101 MOV R1,#0x1
0000004E 4208 TST R0,R1
00000050 D000 BEQ L_15 ; T=0x00000054
50: while ( 1 ); /* Write enable can't be latched, permanent error */
00000052 L_7:
00000052 E7FE B L_7 ; T=0x00000052
53: for ( i = 0; i < BUFSIZE; i++ ) /* Init RD and WR buffer */
00000054 L_15:
00000054 2400 MOV R4,#0x0
00000056 L_14:
55: SPIWRData[i+4] = i; /* leave 4 bytes for cmd and addr */
00000056 1C20 MOV R0,R4 ; i
00000058 0600 LSL R0,R0,#0x18 ; i
0000005A 0E00 LSR R0,R0,#0x18
0000005C 1C22 MOV R2,R4 ; i
0000005E 3204 ADD R2,#0x4
00000060 4800 LDR R1,=SPIWRData ; SPIWRData
00000062 5488 STRB R0,[R1,R2]
57: SPIRDData[i] = 0;
00000064 2000 MOV R0,#0x0
00000066 1C22 MOV R2,R4 ; i
00000068 4800 LDR R1,=SPIRDData ; SPIRDData
0000006A 5488 STRB R0,[R1,R2]
58: }
0000006C 3401 ADD R4,#0x1
0000006E 1C20 MOV R0,R4 ; i
00000070 280A CMP R0,#0xA ; i
00000072 D3F0 BCC L_14 ; T=0x00000056
63: IOCLR0 = SPI0_SEL;
00000074 2180 MOV R1,#0x80
00000076 4800 LDR R0,=0xE002800C
00000078 6001 STR R1,[R0,#0x0]
64: SPIWRData[0] = WRITE; /* Write command is 0x02, low 256 bytes only */
0000007A 2102 MOV R1,#0x2
0000007C 4800 LDR R0,=SPIWRData ; SPIWRData
0000007E 7001 STRB R1,[R0,#0x0] ; SPIWRData
65: SPIWRData[1] = 0x00; /* write high address offset is 0x00 */
00000080 2100 MOV R1,#0x0
00000082 4800 LDR R0,=SPIWRData + 0x1 ; SPIWRData+1
00000084 7001 STRB R1,[R0,#0x0] ; SPIWRData+1
66: SPIWRData[2] = 0x00; /* write middle address offset is 0x00 */
00000086 2100 MOV R1,#0x0
00000088 4800 LDR R0,=SPIWRData + 0x2 ; SPIWRData+2
0000008A 7001 STRB R1,[R0,#0x0] ; SPIWRData+2
67: SPIWRData[3] = 0x00; /* write low address offset is 0x00 */
0000008C 2100 MOV R1,#0x0
0000008E 4800 LDR R0,=SPIWRData + 0x3 ; SPIWRData+3
00000090 7001 STRB R1,[R0,#0x0] ; SPIWRData+3
69: SPISend( SPIWRData, BUFSIZE );
00000092 4800 LDR R0,=SPIWRData ; SPIWRData
00000094 210A MOV R1,#0xA
00000096 F7FF BL SPISend?T ; T=0x0001 (1)
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 6
00000098 FFB3 BL SPISend?T ; T=0x0001 (2)
70: IOSET0 = SPI0_SEL;
0000009A 2180 MOV R1,#0x80
0000009C 4800 LDR R0,=0xE0028004
0000009E 6001 STR R1,[R0,#0x0]
72: for ( i = 0; i < DELAY_COUNT; i++ ); /* delay, minimum 250ns */
000000A0 2400 MOV R4,#0x0
000000A2 L_16:
000000A2 3401 ADD R4,#0x1
000000A4 1C20 MOV R0,R4 ; i
000000A6 280A CMP R0,#0xA ; i
000000A8 D3FB BCC L_16 ; T=0x000000A2
73: timeout = 0;
000000AA 2500 MOV R5,#0x0
000000AC ---- Variable 'timeout' assigned to Register 'R5' ----
74: while ( timeout < MAX_TIMEOUT )
000000AC L_23:
76: IOCLR0 = SPI0_SEL;
000000AC 2180 MOV R1,#0x80
000000AE 4800 LDR R0,=0xE002800C
000000B0 6001 STR R1,[R0,#0x0]
77: SPICmd[0] = RDSR; /* check status to see if write cycle is done or not */
000000B2 2105 MOV R1,#0x5
000000B4 4800 LDR R0,=SPICmd ; SPICmd
000000B6 7001 STRB R1,[R0,#0x0] ; SPICmd
78: SPISend( SPICmd, 1);
000000B8 4800 LDR R0,=SPICmd ; SPICmd
000000BA 2101 MOV R1,#0x1
000000BC F7FF BL SPISend?T ; T=0x0001 (1)
000000BE FFA0 BL SPISend?T ; T=0x0001 (2)
79: SPIReceive( SPIRDData, 1 );
000000C0 4800 LDR R0,=SPIRDData ; SPIRDData
000000C2 2101 MOV R1,#0x1
000000C4 F7FF BL SPIReceive?T ; T=0x0001 (1)
000000C6 FF9C BL SPIReceive?T ; T=0x0001 (2)
80: IOSET0 = SPI0_SEL;
000000C8 2180 MOV R1,#0x80
000000CA 4800 LDR R0,=0xE0028004
000000CC 6001 STR R1,[R0,#0x0]
82: if ( (SPIRDData[0] & RDSR_RDY) == 0x00 ) /* bit 0 to 0 is ready */
000000CE 4800 LDR R0,=SPIRDData ; SPIRDData
000000D0 7800 LDRB R0,[R0,#0x0] ; SPIRDData
000000D2 2101 MOV R1,#0x1
000000D4 4208 TST R0,R1
000000D6 D003 BEQ L_22 ; T=0x000000E0
86: timeout++;
000000D8 3501 ADD R5,#0x1
87: }
000000DA 1C28 MOV R0,R5 ; timeout
000000DC 28FF CMP R0,#0xFF ; timeout
000000DE D3E5 BCC L_23 ; T=0x000000AC
000000E0 L_22:
88: if ( timeout == MAX_TIMEOUT )
000000E0 1C28 MOV R0,R5 ; timeout
000000E2 28FF CMP R0,#0xFF ; timeout
000000E4 D100 BNE L_35 ; T=0x000000E8
90: while ( 1 );
000000E6 L_27:
000000E6 E7FE B L_27 ; T=0x000000E6
93: for ( i = 0; i < DELAY_COUNT; i++ ); /* delay, minimum 250ns */
000000E8 L_35:
000000E8 2400 MOV R4,#0x0
000000EA L_31:
000000EA 3401 ADD R4,#0x1
000000EC 1C20 MOV R0,R4 ; i
000000EE 280A CMP R0,#0xA ; i
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 7
000000F0 D3FB BCC L_31 ; T=0x000000EA
94: IOCLR0 = SPI0_SEL;
000000F2 2180 MOV R1,#0x80
000000F4 4800 LDR R0,=0xE002800C
000000F6 6001 STR R1,[R0,#0x0]
95: SPICmd[0] = READ; /* Read command is 0x03, low 256 bytes only */
000000F8 2103 MOV R1,#0x3
000000FA 4800 LDR R0,=SPICmd ; SPICmd
000000FC 7001 STRB R1,[R0,#0x0] ; SPICmd
96: SPICmd[1] = 0x00; /* write high address offset is 0x00 */
000000FE 2100 MOV R1,#0x0
00000100 4800 LDR R0,=SPICmd + 0x1 ; SPICmd+1
00000102 7001 STRB R1,[R0,#0x0] ; SPICmd+1
97: SPICmd[2] = 0x00; /* write middle address offset is 0x00 */
00000104 2100 MOV R1,#0x0
00000106 4800 LDR R0,=SPICmd + 0x2 ; SPICmd+2
00000108 7001 STRB R1,[R0,#0x0] ; SPICmd+2
98: SPICmd[3] = 0x00; /* write low address offset is 0x00 */
0000010A 2100 MOV R1,#0x0
0000010C 4800 LDR R0,=SPICmd + 0x3 ; SPICmd+3
0000010E 7001 STRB R1,[R0,#0x0] ; SPICmd+3
99: SPISend( SPICmd, 4 );
00000110 4800 LDR R0,=SPICmd ; SPICmd
00000112 2104 MOV R1,#0x4
00000114 F7FF BL SPISend?T ; T=0x0001 (1)
00000116 FF74 BL SPISend?T ; T=0x0001 (2)
100: SPIReceive( SPIRDData+4, BUFSIZE-4 );
00000118 4800 LDR R0,=SPIRDData + 0x4 ; SPIRDData+4
0000011A 2106 MOV R1,#0x6
0000011C F7FF BL SPIReceive?T ; T=0x0001 (1)
0000011E FF70 BL SPIReceive?T ; T=0x0001 (2)
101: IOSET0 = SPI0_SEL;
00000120 2180 MOV R1,#0x80
00000122 4800 LDR R0,=0xE0028004
00000124 6001 STR R1,[R0,#0x0]
104: for ( i = 4; i < BUFSIZE; i++ )
00000126 2404 MOV R4,#0x4
00000128 L_39:
106: if ( SPIWRData[i] != SPIRDData[i] )
00000128 1C21 MOV R1,R4 ; i
0000012A 4800 LDR R0,=SPIRDData ; SPIRDData
0000012C 5C40 LDRB R0,[R0,R1]
0000012E 1C01 MOV R1,R0
00000130 1C22 MOV R2,R4 ; i
00000132 4800 LDR R0,=SPIWRData ; SPIWRData
00000134 5C80 LDRB R0,[R0,R2]
00000136 4288 CMP R0,R1
00000138 D000 BEQ L_36 ; T=0x0000013C
108: while( 1 ); /* Verification failed */
0000013A L_42:
0000013A E7FE B L_42 ; T=0x0000013A
110: }
0000013C L_36:
0000013C 3401 ADD R4,#0x1
0000013E 1C20 MOV R0,R4 ; i
00000140 280A CMP R0,#0xA ; i
00000142 D3F1 BCC L_39 ; T=0x00000128
111: return;
00000144 ; SCOPE-END
112: }
00000144 BC30 POP {R4-R5}
00000146 BC08 POP {R3}
00000148 4718 BX R3
0000014A ENDP ; 'SPI0_Test?T'
*** CODE SEGMENT '?PR?main?spitest':
117: int main (void)
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 8
00000000 B500 PUSH {LR}
119: init_VIC();
00000002 F7FF BL init_VIC?T ; T=0x0001 (1)
00000004 FFFD BL init_VIC?T ; T=0x0001 (2)
121: SPIInit(); /* initialize SPI 0 */
00000006 F7FF BL SPIInit?T ; T=0x0001 (1)
00000008 FFFB BL SPIInit?T ; T=0x0001 (2)
122: SPI0_Test();
0000000A F7FF BL SPI0_Test?T ; T=0x0001 (1)
0000000C FFF9 BL SPI0_Test?T ; T=0x0001 (2)
123: return 0;
0000000E 2000 MOV R0,#0x0
124: }
00000010 BC08 POP {R3}
00000012 4718 BX R3
00000014 ENDP ; 'main'
Module Information Static
----------------------------------
code size = ------
data size = 30
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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