📄 spitest.lst
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ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 1
ARM COMPILER V2.53, COMPILATION OF MODULE spitest
OBJECT MODULE PLACED IN .\Obj\spitest.obj
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe spitest.c THUMB INCDIR(..\Common\inc) DEBUG PRINT(.\LST\SPITEST.LST) TABS(4)
- OBJECT(.\Obj\spitest.obj)
stmt level source
1 /*****************************************************************************
2 * spitest.c: main C entry file for Philips LPC214x Family Microprocessors
3 *
4 * Copyright(C) 2006, Philips Semiconductor
5 * All rights reserved.
6 *
7 * History
8 * 2005.10.01 ver 1.00 Prelimnary version, first Release
9 *
10 ******************************************************************************/
11 #include "LPC214x.H" /* LPC21xx definitions */
12 #include "type.h"
13 #include "irq.h"
14 #include "spi.h"
15
16 BYTE SPICmd[BUFSIZE];
17 BYTE SPIWRData[BUFSIZE];
18 BYTE SPIRDData[BUFSIZE];
19
20 /*****************************************************************************
21 ** Function name: SPI0_Test
22 **
23 ** Descriptions: Test SPI0 as master interfacing with a Atmel
24 ** SPI based Serial EEPROM 25020
25 **
26 ** parameters: None
27 ** Returned value: None
28 **
29 *****************************************************************************/
30 void SPI0_Test( void )
31 {
32 1 DWORD i, timeout;
33 1
34 1 IOCLR0 = SPI0_SEL;
35 1 /* The tested SPI device is a Atmel 25020 */
36 1 SPICmd[0] = WREN; /* set write enable latch */
37 1 SPISend( SPICmd, 1 );
38 1 IOSET0 = SPI0_SEL;
39 1
40 1 for ( i = 0; i < DELAY_COUNT; i++ ); /* delay minimum 250ns */
41 1
42 1 IOCLR0 = SPI0_SEL;
43 1 SPICmd[0] = RDSR; /* check status to see if write enabled is latched */
44 1 SPISend( SPICmd, 1 );
45 1 SPIReceive( SPIRDData, 1 );
46 1 IOSET0 = SPI0_SEL;
47 1 if ( SPIRDData[0] & (RDSR_WEN|RDSR_RDY) != RDSR_WEN )
48 1 /* bit 0 to 0 is ready, bit 1 to 1 is write enable */
49 1 {
50 2 while ( 1 ); /* Write enable can't be latched, permanent error */
51 2 }
52 1
53 1 for ( i = 0; i < BUFSIZE; i++ ) /* Init RD and WR buffer */
54 1 {
55 2 SPIWRData[i+4] = i; /* leave 4 bytes for cmd and addr */
56 2 /* byte 0 and 1 are used for commands and offset */
57 2 SPIRDData[i] = 0;
58 2 }
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 2
59 1
60 1 /* please note the first two bytes of WR and RD buffer is used for
61 1 commands and offset, so only 2 through BUFSIZE is used for data read,
62 1 write, and comparison. */
63 1 IOCLR0 = SPI0_SEL;
64 1 SPIWRData[0] = WRITE; /* Write command is 0x02, low 256 bytes only */
65 1 SPIWRData[1] = 0x00; /* write high address offset is 0x00 */
66 1 SPIWRData[2] = 0x00; /* write middle address offset is 0x00 */
67 1 SPIWRData[3] = 0x00; /* write low address offset is 0x00 */
68 1
69 1 SPISend( SPIWRData, BUFSIZE );
70 1 IOSET0 = SPI0_SEL;
71 1
72 1 for ( i = 0; i < DELAY_COUNT; i++ ); /* delay, minimum 250ns */
73 1 timeout = 0;
74 1 while ( timeout < MAX_TIMEOUT )
75 1 {
76 2 IOCLR0 = SPI0_SEL;
77 2 SPICmd[0] = RDSR; /* check status to see if write cycle is done or not */
78 2 SPISend( SPICmd, 1);
79 2 SPIReceive( SPIRDData, 1 );
80 2 IOSET0 = SPI0_SEL;
81 2
82 2 if ( (SPIRDData[0] & RDSR_RDY) == 0x00 ) /* bit 0 to 0 is ready */
83 2 {
84 3 break;
85 3 }
86 2 timeout++;
87 2 }
88 1 if ( timeout == MAX_TIMEOUT )
89 1 {
90 2 while ( 1 );
91 2 }
92 1
93 1 for ( i = 0; i < DELAY_COUNT; i++ ); /* delay, minimum 250ns */
94 1 IOCLR0 = SPI0_SEL;
95 1 SPICmd[0] = READ; /* Read command is 0x03, low 256 bytes only */
96 1 SPICmd[1] = 0x00; /* write high address offset is 0x00 */
97 1 SPICmd[2] = 0x00; /* write middle address offset is 0x00 */
98 1 SPICmd[3] = 0x00; /* write low address offset is 0x00 */
99 1 SPISend( SPICmd, 4 );
100 1 SPIReceive( SPIRDData+4, BUFSIZE-4 );
101 1 IOSET0 = SPI0_SEL;
102 1
103 1 /* verifying, ignore the difference in the first two bytes */
104 1 for ( i = 4; i < BUFSIZE; i++ )
105 1 {
106 2 if ( SPIWRData[i] != SPIRDData[i] )
107 2 {
108 3 while( 1 ); /* Verification failed */
109 3 }
110 2 }
111 1 return;
112 1 }
113
114 /******************************************************************************
115 ** Main Function main()
116 ******************************************************************************/
117 int main (void)
118 {
119 1 init_VIC();
120 1
121 1 SPIInit(); /* initialize SPI 0 */
122 1 SPI0_Test();
123 1 return 0;
124 1 }
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 3
125
126 /******************************************************************************
127 ** End Of File
128 ******************************************************************************/
129
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 4
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN CODE16 (init_VIC?T)
EXTERN CODE16 (SPIInit?T)
EXTERN CODE16 (SPISend?T)
EXTERN CODE16 (SPIReceive?T)
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC SPI0_Test?T
PUBLIC main
PUBLIC SPICmd
PUBLIC SPIWRData
PUBLIC SPIRDData
*** DATA SEGMENT '?DT0?spitest':
00000000 SPICmd:
00000000 DS 10
0000000A SPIWRData:
0000000A DS 10
00000014 SPIRDData:
00000014 DS 10
*** CODE SEGMENT '?PR?SPI0_Test?T?spitest':
30: void SPI0_Test( void )
00000000 B530 PUSH {R4-R5,LR}
31: {
00000002 ; SCOPE-START
34: IOCLR0 = SPI0_SEL;
00000002 2180 MOV R1,#0x80
00000004 4800 LDR R0,=0xE002800C
00000006 6001 STR R1,[R0,#0x0]
36: SPICmd[0] = WREN; /* set write enable latch */
00000008 2106 MOV R1,#0x6
0000000A 4800 LDR R0,=SPICmd ; SPICmd
0000000C 7001 STRB R1,[R0,#0x0] ; SPICmd
37: SPISend( SPICmd, 1 );
0000000E 4800 LDR R0,=SPICmd ; SPICmd
00000010 2101 MOV R1,#0x1
00000012 F7FF BL SPISend?T ; T=0x0001 (1)
00000014 FFF5 BL SPISend?T ; T=0x0001 (2)
38: IOSET0 = SPI0_SEL;
00000016 2180 MOV R1,#0x80
00000018 4800 LDR R0,=0xE0028004
0000001A 6001 STR R1,[R0,#0x0]
40: for ( i = 0; i < DELAY_COUNT; i++ ); /* delay minimum 250ns */
0000001C 2400 MOV R4,#0x0
0000001E ---- Variable 'i' assigned to Register 'R4' ----
0000001E L_1:
0000001E 3401 ADD R4,#0x1
00000020 1C20 MOV R0,R4 ; i
00000022 280A CMP R0,#0xA ; i
00000024 D3FB BCC L_1 ; T=0x0000001E
42: IOCLR0 = SPI0_SEL;
00000026 2180 MOV R1,#0x80
00000028 4800 LDR R0,=0xE002800C
0000002A 6001 STR R1,[R0,#0x0]
43: SPICmd[0] = RDSR; /* check status to see if write enabled is latched */
0000002C 2105 MOV R1,#0x5
0000002E 4800 LDR R0,=SPICmd ; SPICmd
00000030 7001 STRB R1,[R0,#0x0] ; SPICmd
44: SPISend( SPICmd, 1 );
00000032 4800 LDR R0,=SPICmd ; SPICmd
00000034 2101 MOV R1,#0x1
ARM COMPILER V2.53, spitest 19/12/07 10:53:13 PAGE 5
00000036 F7FF BL SPISend?T ; T=0x0001 (1)
00000038 FFE3 BL SPISend?T ; T=0x0001 (2)
45: SPIReceive( SPIRDData, 1 );
0000003A 4800 LDR R0,=SPIRDData ; SPIRDData
0000003C 2101 MOV R1,#0x1
0000003E F7FF BL SPIReceive?T ; T=0x0001 (1)
00000040 FFDF BL SPIReceive?T ; T=0x0001 (2)
46: IOSET0 = SPI0_SEL;
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