haha.txt

大开杀戒何妨神侃的军火库计算的话付款及时电话访客技术 大法师的

程序说明：1。此程序包括分频，计数控制，显示控制部分。
2。开机显示00。00。00，用户课随时计时，暂停，清零，最大计时可到59 分59。99秒。
3。技术时钟为100HZ
4。采用时分复用的方法控制4个数码管的显示，可节省资源。
程序如下：
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all; 
Use ieee.std_logic_unsigned.all;
Entity watch is
Port(sel: out std_logic_vector(6 downto 1) ;
seg:out std_logic_vector(7 downto 0);
Beginstop:in std_logic;
Reset:in std_logic;
Cp2:in std_logic);
End watch;
Architecture behave of watch is
Signal num1: std_logic_vector(3 downto 0);
Signal num2: std_logic_vector(3 downto 0);
Signal num3: std_logic_vector(3 downto 0);
Signal num4: std_logic_vector(3 downto 0);
Signal num5: std_logic_vector(3 downto 0);
Signal num6: std_logic_vector(3 downto 0);
Signal num: std_logic_vector(3 downto 0);
Signal numlet: std_logic_vector(2 downto 0);
Signal count: std_logic_vector(17 downto 1);
Signal selsig: std_logic_vector(6 downto 1);
Signal segsig: std_logic_vector(7 downto 0 );
Signal cp1: std_logic;
Signal cp3: std_logic;
Begin
Process(cp2) ---- 分频。
Begin 
If (cp2' event and cp2='1') then 
if (Count="1100011010011111")then
count<="00000000000000000"; cp1<=not cp1;
else count<=count 1;
end if;
end if;
cp3<=count(10);
end process;
process(cp1)
begin 
if reset ='1' then num1(3 downto 0) <="0000";
num2(3 downto 0) <="0000";
num3(3 downto 0) <="0000";
num4(3 downto 0) <="0000";
num5(3 downto 0) <="0000";
num6(3 downto 0) <="0000";

else if cp1' event and cp1='1' then 
if beginstop='1' then num1<=num1 1;
if num1 (3 downto 0)="1001" then 
num1 (3 downto 0)<="0000"; num2<= num2 1;
if num2 (3 downto 0)="1001" then 
num2 (3 downto 0)<="0000"; num3<= num3 1;
if num3 (3 downto 0)="1001" then 
num3 (3 downto 0)<="0000"; num4<= num4 1;
if num4 (3 downto 0)="0101" then 
num4 (3 downto 0)<="0000"; num5<= num5 1;
if num5 (3 downto 0)="1001" then 
num5 (3 downto 0)<="0000"; num6<= num6 1;
if num6 (3 downto 0)="0101" then 
num6(3 downto 0)<="0000";
end if; end if; end if; end if; end if; end if; end if;
end if; end if;
end process;
process (cp3) 
begin 
if (cp3' event and cp3='1')then 
if(numlet(2 downto 0)="000") then
num<=num1;selsig(6 downto 1)<="111110"; end if;
if(numlet(2 downto 0)="001") then
num<=num2;selsig(6 downto 1)<="111101"; end if;
if(numlet(2 downto 0)="010") then
num<=num3;selsig(6 downto 1)<="111011"; end if;
if(numlet(2 downto 0)="011") then
num<=num4;selsig(6 downto 1)<="110111"; end if;
if(numlet(2 downto 0)="100") then
num<=num5;selsig(6 downto 1)<="101111"; end if;
numlet(2 downto 0)<=numlet(2 downto 0) 1;
if(numlet(2 downto 0)="101") then
numlet(2 downto 0)<="011111"; end if;
end if;
if (num (3 downto 0)="0000")then 
segsig(7 downto 0)<="01111111"; end if;
if (num (3 downto 0)="0001")then 
segsig(7 downto 0)<="00001101"; end if;
if (num (3 downto 0)="0010")then 
segsig(7 downto 0)<="10110111"; end if;
if (num (3 downto 0)="0011")then 
segsig(7 downto 0)<="10011111"; end if;
if (num (3 downto 0)="0100")then 
segsig(7 downto 0)<="11001101"; end if;
if (num (3 downto 0)="0101")then 
segsig(7 downto 0)<="11011011"; end if;
if (num (3 downto 0)="0110")then 
segsig(7 downto 0)<="11111011"; end if;
if (num (3 downto 0)="0111")then 
segsig(7 downto 0)<="00001111"; end if;
if (num (3 downto 0)="1000")then 
segsig(7 downto 0)<="11111111"; end if;
if (num (3 downto 0)="1001")then 
segsig(7 downto 0)<="11011111"; end if;
end process;
sel<=selsig;
seg(7 downto 0)<=segsig(7 downto 0);
end behave; 






本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片，用VHDL语言描述的。它除开关、时钟和显示功能以外，它还包括1/100s计时器所有的控制和定时功能，其体积小，携带方便。

计时器的设计功能：

（1）  精度应大于1/100s

（2）  计时器的最长计时时间为1小时

       在一般的短时间计时应用中，1小时应该足够了。为此需要一个6位显示器，显示最长时间为59分59.99秒。

（3）  设置复位和启/停开关

       复位开关用来使计时器清0，并作好清0准备。启/停开关的使用方法与传统的机械计时器相同，即按一下启/停开关，启动计时器开始计时，再按一下启/停开关计时终止。复位开关可以在任何情况下使用，即使在计时过程中，只要按一下复位开关，计时进程应立即终止，并对计时器清零。

设计方案：

    为了便于描述，将整个计时控制芯片分成5个子模块：键输入子模块（keyin）,时钟产生子模块（clkgen）,控制子模块（ctrl）,定时计数子模块（cntclk）和显示子模块（disp）,各模块之间信号连接关系的方框图如下：

芯片设计：

各模块程序及生成的符号文件如下：

keyin模块设计

该模块的描述是为了产生单个复位脉冲res和启停脉冲stst.整个功能模块用两个进程语句描述。

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity keyin is

port(reset,start_stop,clk :in std_logic;

res,stst :out std_logic);

end entity;

architecture a of keyin is

signal res0,res1,stst0,stst1 :std_logic;

begin

process(clk)

begin

if(clk'event and clk='0')then

 res1<=res0;

 res0<=reset;

 stst1<=stst0;

 stst0<=start_stop;

end if;

end process;

process(res0,res1,stst0,stst1)

begin

res<=clk and res0 and (not res1);

stst<=clk and stst0 and (not stst1);

end process;

end a;

clkgen模块设计

该模块的功能是产生100Hz的计时允许信号cntclk和25Hz的宽度为1ms的键输入时钟信号keycek.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY cnt10 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry:OUT STD_LOGIC;

          q    :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT10;

 

ARCHITECTURE rtl OF cnt10 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1') THEN

              IF(qs="1001") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="1000") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY cnt4 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry       :OUT STD_LOGIC;

          q           :OUT STD_LOGIC_VECTOR(1 DOWNTO 0));

END CNT4;

 

ARCHITECTURE rtl OF cnt4 IS

     SIGNAL qs :STD_LOGIC_VECTOR(1 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="00";

          ELSIF (EN='1')THEN

              IF(qs="11") THEN

                qs<= "00";

                ca<='0';

              ELSIF(qs="10") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;

 

   

ctrl子模块

该模块的功能是产生计时计数模块的计数允许信号cnten

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity ctrl is

port(sysres,res,stst,cntclk:in std_ulogic;

centen:out std_ulogic);

end ctrl;

architecture rtl of ctrl is

signal enb1:std_ulogic;

begin

process(stst,sysres,res)

begin

if(sysres='1' or res='1') then

enb1<='0';

elsif(stst'event and stst='1') then

enb1<=not enb1;

end if;

end process;

centen<=enb1 and cntclk;

end rtl;

cntblk模块设计

该模块的功能是实现计时计数，它由四个十进制计数器和两个六进制计数器串结而成。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY cnt10 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry:OUT STD_LOGIC;

          q    :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT10;

 

ARCHITECTURE rtl OF cnt10 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1') THEN

              IF(qs="1001") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="1000") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca,en)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;

   

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

 

ENTITY cnt6 IS

    PORT (reset,en,clk:IN STD_LOGIC;

          carry       :OUT STD_LOGIC;

          q           :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END CNT6;

 

ARCHITECTURE rtl OF cnt6 IS

     SIGNAL qs :STD_LOGIC_VECTOR(3 DOWNTO 0);

     SIGNAL ca :STD_LOGIC;

BEGIN

    PROCESS(clk)

      BEGIN

       IF(clk'EVENT AND clk='1')THEN

          IF(reset='1')THEN

              qs<="0000";

          ELSIF(en='1')THEN

              IF(qs="0101") THEN

                qs<= "0000";

                ca<='0';

              ELSIF(qs="0100") THEN

                qs<= qs+1;

                ca<='1';

              ELSE

                qs<=qs+1;

                ca<='0';

              END IF;

          END IF;

       END IF;

      END PROCESS;

     PROCESS(ca,en)

     BEGIN

        q<=qs;

        carry<=ca AND en;

     END PROCESS;

  END rtl;