motfecend.h

ADS88x BSP

/* motFecEnd.h - Motorola FEC Ethernet network interface header */

/* Copyright 1990-2005 Wind River Systems, Inc. */
/* Copyright 1999-2000 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01j,10apr05,mig  Fix compile warnings. SPR# 107245
01i,18nov04,dtr  Remove cacheArchXXX usage.
01h,24feb04,dtr  Added support for FEC2 specifically for MPC885.
01g,01apr02,pmr  SPR 72070: passing unit number to sysFecEnetAddrGet.
01f,07dec01,rcs  added  define REV_D_3 SPR# 71420  
01e,26oct01,crg  added support for proper setting of MII management interface
                 speed (SPR 33812)
01d,21nov00,rhk  added define for revision D4 processor and for pin mux bit.
01c,11jun00,ham  removed reference to etherLib.
01b,09feb99,cn	 changes required by performance improvement (SPR# 24883).
01a,09nov98,cn	 written.
*/

#ifndef __INCmotFecEndh
#define __INCmotFecEndh

/* includes */

#ifdef __cplusplus
extern "C" {
#endif

/* defines */

/* revision D.3 and greater processors require special FEC initialization */

#define REV_D_4 0x0502
#define REV_D_3 0x0501

/*
 * redefine the macro below in the bsp if you need to access the device
 * registers/descriptors in a more suitable way.
 */

#ifndef MOT_FEC_LONG_WR
#define MOT_FEC_LONG_WR(addr, value)                                        \
    (* (addr) = ((UINT32) (value)))
#endif /* MOT_FEC_LONG_WR */

#ifndef MOT_FEC_WORD_WR
#define MOT_FEC_WORD_WR(addr, value)                                        \
    (* (addr) = ((UINT16) (value)))
#endif /* MOT_FEC_WORD_WR */

#ifndef MOT_FEC_BYTE_WR
#define MOT_FEC_BYTE_WR(addr, value)                                        \
    (* (addr) = ((UINT8) (value)))
#endif /* MOT_FEC_BYTE_WR */

#ifndef MOT_FEC_LONG_RD
#define MOT_FEC_LONG_RD(addr, value)                                        \
    ((value) = (* (UINT32 *) (addr)))
#endif /* MOT_FEC_LONG_RD */

#ifndef MOT_FEC_WORD_RD
#define MOT_FEC_WORD_RD(addr, value)                                        \
    ((value) = (* (UINT16 *) (addr)))
#endif /* MOT_FEC_WORD_RD */

#ifndef MOT_FEC_BYTE_RD
#define MOT_FEC_BYTE_RD(addr, value)                                        \
    ((value) = (* (UINT8 *) (addr)))
#endif /* MOT_FEC_BYTE_RD */

/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */

#ifndef SYS_FEC_INT_CONNECT
#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFunc, arg, ret)                      \
{                                                                           \
IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);		    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) && (!(pDrvCtrl->intrConnect)))  		    \
    {                                                                       \
    pDrvCtrl->intrConnect = TRUE;                                   	    \
    ret = (intConnect) ((VOIDFUNCPTR*)                              	    \
                                INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)),   \
                                (pFunc), (int) (arg));                      \
    }                                                                       \
}

#endif /* SYS_FEC_INT_CONNECT */

#ifndef SYS_FEC_INT_DISCONNECT
#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFunc, arg, ret)                   \
{                                                                           \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) && (motFecIntDisc != NULL))             	    \
    {                                                                       \
    pDrvCtrl->intrConnect = FALSE;                                          \
    ret = (*motFecIntDisc) ((VOIDFUNCPTR*)                          	    \
                              INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)),     \
                              (pFunc));                                     \
    }                                                                       \
}
#endif /* SYS_FEC_INT_DISCONNECT */

#ifndef SYS_FEC_INT_ENABLE
#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intEnable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intEnable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_ENABLE */

#ifndef SYS_FEC_INT_DISABLE
#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intDisable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intDisable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_DISABLE */

#define SYS_FEC_ENET_ADDR_GET(address)                                  \
if (sysFecEnetAddrGet != NULL)                                          \
    if (sysFecEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)         \
        {                                                               \
        errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);                   \
        return (NULL);                                                  \
        }

#define SYS_FEC_ENET_ENABLE                                             \
if (sysFecEnetEnable != NULL)                                           \
    if (sysFecEnetEnable (pDrvCtrl->motCpmAddr,pDrvCtrl->fecNum) == ERROR)               \
        return (ERROR);

#define SYS_FEC_ENET_DISABLE                                            \
if (sysFecEnetDisable != NULL)                                          \
    if (sysFecEnetDisable (pDrvCtrl->motCpmAddr,pDrvCtrl->fecNum) == ERROR)              \
        return (ERROR);

#define MOT_FEC_DEV_NAME       	"motfec"
#define MOT_FEC_DEV_NAME_LEN   	7
#define MOT_FEC_TBD_DEF_NUM    	64		/* default number of TBDs */
#define MOT_FEC_RBD_DEF_NUM    	48		/* default number of RBDs */
#define MOT_FEC_TX_CL_NUM    	6		/* number of tx clusters */
#define MOT_FEC_BD_LOAN_NUM    	32		/* loaned BDs */
#define MOT_FEC_TBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_RBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_WAIT_MAX	0xf0000000	/* max delay after sending */

#define MOT_FEC_ADDR_LEN        6               /* ethernet address length */

/* Control/Status Registers (CSR) definitions */
/* This structure is pointed directly at the device registers and used 
   primarily to calculate offsets from the device base address. Means very 
   few changes in main driver file to support two devices */ 
typedef struct fecDevice {
  UINT32 addr_l;
  UINT32 addr_h;
  UINT32 hash_h;
  UINT32 hash_l;
  UINT32 rx_start;
  UINT32 tx_start;
  UINT32 rx_buf;
  UINT32 pad1[0x9];
  UINT32 ctrl;
  UINT32 event;
  UINT32 mask;
  UINT32 vec;
  UINT32 rx_act;
  UINT32 tx_act;
  UINT32 pad2[0xa];
  UINT32 mii_data;
  UINT32 mii_speed;
  UINT32 pad3[0x11];
  UINT32 rx_bound;
  UINT32 rx_fifo;
  UINT32 pad4[0x6];
  UINT32 tx_fifo;
  UINT32 pad5[0x11];
  UINT32 sdma;
  UINT32 pad6[0x3];
  UINT32 rx_ctrl;
  UINT32 rx_fr;
  UINT32 pad7[0xf];
  UINT32 tx_ctrl;
} FEC_DEVICE;


#define MOT_FEC_CSR_OFF         pDrvCtrl->pFecDevice->addr_l  /* CSRs offset in the 860T RAM */
#define MOT_FEC_ADDR_L_OFF      pDrvCtrl->pFecDevice->addr_l  /* lower 32-bits of MAC address */
#define MOT_FEC_ADDR_H_OFF      pDrvCtrl->pFecDevice->addr_h  /* upper 16-bits of MAC address */
#define MOT_FEC_HASH_H_OFF      pDrvCtrl->pFecDevice->hash_h  /* upper 32-bits of hash table */
#define MOT_FEC_HASH_L_OFF      pDrvCtrl->pFecDevice->hash_l  /* lower 32-bits of hash table */
#define MOT_FEC_RX_START_OFF    pDrvCtrl->pFecDevice->rx_start  /* rx ring start address */
#define MOT_FEC_TX_START_OFF    pDrvCtrl->pFecDevice->tx_start  /* tx ring start address */
#define MOT_FEC_RX_BUF_OFF      pDrvCtrl->pFecDevice->rx_buf  /* max rx buf length */
#define MOT_FEC_CTRL_OFF        pDrvCtrl->pFecDevice->ctrl  /* FEC control register */
#define MOT_FEC_EVENT_OFF       pDrvCtrl->pFecDevice->event  /* interrupt event register */
#define MOT_FEC_MASK_OFF        pDrvCtrl->pFecDevice->mask  /* interrupt mask register */
#define MOT_FEC_VEC_OFF         pDrvCtrl->pFecDevice->vec  /* interrupt level/vector register */
#define MOT_FEC_RX_ACT_OFF      pDrvCtrl->pFecDevice->rx_act  /* rx ring has been updated */
#define MOT_FEC_TX_ACT_OFF      pDrvCtrl->pFecDevice->tx_act  /* tx ring has been updated */


#if 0  /* Errata of 885 chip doesn't support FEC2 MII registers */
#define MOT_FEC_MII_DATA_OFF    pDrvCtrl->pFecDevice->mii_data  /* MII data register */
#define MOT_FEC_MII_SPEED_OFF   pDrvCtrl->pFecDevice->mii_speed  /* MII speed register */
#endif

#define MOT_FEC_RX_BOUND_OFF    pDrvCtrl->pFecDevice->rx_bound  /* rx fifo limit in the 860T ram */
#define MOT_FEC_RX_FIFO_OFF     pDrvCtrl->pFecDevice->rx_fifo  /* rx fifo base in the 860T ram */
#define MOT_FEC_TX_FIFO_OFF     pDrvCtrl->pFecDevice->tx_fifo  /* tx fifo base in the 860T ram */
#define MOT_FEC_SDMA_OFF        pDrvCtrl->pFecDevice->sdma  /* function code to SDMA */
#define MOT_FEC_RX_CTRL_OFF     pDrvCtrl->pFecDevice->rx_ctrl  /* rx control register */
#define MOT_FEC_RX_FR_OFF       pDrvCtrl->pFecDevice->rx_fr  /* max rx frame length */
#define MOT_FEC_TX_CTRL_OFF     pDrvCtrl->pFecDevice->tx_ctrl  /* tx control register */