target.ref

ADS88x BSP

\" ads88x/target.ref - Motorola MPC8xx(F)ADS target specific documentation
\"
\" Copyright 1984-2003 Wind River Systems, Inc.
\"
\" modification history
\" --------------------
\" 01b,22mar05,mig  Fix apigen warnings.
\" 01a,16feb04,dtr  created from ads860.
\"
\"
\TITLE ads88x - Motorola DUET Users Manual

NAME
Motorola DUET & MPC885 ADS 

INTRODUCTION
This note provides board-specific information necessary to run
VxWorks.  Before running VxWorks, verify that the board runs in the
factory configuration.
The ads88x BSP produces a VxWorks image running on either the PowerPC 88x 
processors. From the VxWorks perspective these processors are equivalent.

BOOT ROMS
No VxWorks Boot ROM is provided with this BSP release. Nevertheless VxWorks
boot code is working if downloaded into the SIMM Flash ROM.


\sh Jumpers
SW2/SW4/SW7 settings tested with:
\cs
Pins    SW2     SW4     SW7
1       ON      OFF     OFF
2       ON      OFF     OFF
3       ON      OFF
4       OFF     OFF
\ce




This board doesn't have non-volatile RAM; thus boot parameters
are not preserved when the system is powered off.



To load VxWorks, and for more information, follow the instructions in the
"Getting Started"
chapter of the
\tb VxWorks Programmer's Guide. 

\sh Programming the flash using Vision Click and vision Probe


Connect the JTAG interface cable from the visionPROBE II or
visionICE II into the MPC885 DUET board BDM J21 connector, and power it on.
Once all the connections have been made, power up the and start 
visionCLICK on the host.

	
Configure the visionCLICK project:
The "Welcome To visionCLICK" window will appear.  In this
window press on the "Configure" button, this will invoke
the "PROJECTS/LOAD" window.  In this window press on
the '+' left of the "[e-mail]"
project to expand the project which will show you the
current project configuration.

Point with the mouse cursor on the "Microprocessors" option
and right-click to choose "PowerPC->MPC8xx->MPC885"

Verify that the "Target Control" option points to
visionPROBE for visionPROBE II, or visionICE for
visionICE II.

Switch to the "Communications" TAB and verify that the
"Normal Port/Rate" & "Download Port/Rate" is set to the
correct LPT port if you are using visionPROBE II or enter
the emulator IP address if you are using visionICE
Save the project by clicking the "Save" button at the
bottom of the window. Click the "Activate" button to send
the project configuration to the attached hardware
debugger.


Program visionPROBE II / visionICE II with the proper
register setting for the MPC885 DUET board:
Use the register file "ads885.vsh" in the ads88x BSP directory.
Go to the "Tools" menu and select the "Log Output/Playback
Scripts" option. The "Record / Playback" dialog box will
popup.  Go to the "Playback Commands From File"
group and click the "Browse" button.  Navigate to the
location of the register file: "ads885.vsh".  After
choosing the register file press on the "Open" button to
confirm the selected reg file.  This will return you back
to the "Record / Playback" dialog box.  Click the "Start"
button located in the same group.  In the "Terminal" window
you can see that visionCLICK is running the script.
When the script is finished running, you will get
back the ">BKM>" or the ">ERR>" prompt.


Get into Background Mode:
At the "Terminal" window, execute the "IN" command to reset
the board and initialize it with the register settings.

If initialized properly, you should see >BKM> prompt at the
terminal window as shown below.

\cs
 >ERR>IN
 ***********************************************************
 VisionICE II Initialization Sequence.  Copyright WIND RIVER
 Corp. 2002
 ***********************************************************
 Support Expires..... 1/12/03 Target Processor..... MPC885
 VisionICE II             Group ID#= 0
 VisionICE II    Serial#= N2201100    Firmware=vn2.0a
 Type CF for a Menu of Configuration Options Using
 Front PANEL as BDM source
 Initializing Background Debug Mode..............Successful
 >BKM>
\ce


Ensure that the register file has been loaded to both
the emulator and the target.  Verfiy the values for "OR0",
"BR0", "OR2" and "BR2" shown in the Register window under
"MEMC" group matches the target.  To find out a register
value in the target, in "Terminal" windows, type "DR
name_of_register".  For e.g.

\cs
	 >BKM>DR OR0
			
	 The proper values are:
			
	 OR0 = FFE00D34
	 BR0 = 02800001
	 OR4 = FF800A00
	 BR4 = 000000C1
\ce

Setting the Flash Chip Select:
Once the ">BKM>" prompt appears we need to verify
that the Flash chip select configuration is
correct. To do this, type "CS" at the >BKM>
prompt in the "Terminal" window and press Enter.
The first line ("CS0") is for the Flash chip
select.  Under the "PS" (for Port Size) column for
CS0, check that the number is "32".

Converting bootrom_uncmp.hex to bootrom_uncmp.bin:
In visionCLICK, choose "Convert Object Modules"
from the "Tools" menu.  The "CONVERT BINARY AND
SYMBOL OBJs" window will appear.  Go to the
"Select Input Object Module To Convert"
group and navigate to the file "bootrom_uncmp.hex"
located in "$(WIND_BASE)/target/config/ads88x

In the group "Binary Downloadable Objects Modules"
check the "Create Flat BIN File For Flash
Programming".  "In Range Of 0x" edit box, enter
"0" for the start address, and in the "To 0x" edit
box, enter "FFFFFFFF".

Make sure that none of the other check boxes are
checked.  Press the "Convert" button. Close the
terminal window when the conversion completes.

Programming the Flash:
In visionCLICK, select "Program Flash Devices" from the
Tools pull-down menu and this will invoke the "TF FLASH
PROGRAMMING" window.
Click the "Select" in the "Flash Card or PC Host
File Name and Path" group.  The "CHOOSE A FILE FROM
HOST PC" window will appear.  In the edit box enter
the full path of the file "bootrom_uncmp.bin", or
use the "<--Browse" button to navigate to the file.

Go to the "+/- Bias" group and enter "02800000" in
the edit box. Click the "OK" button. This will
bring you back to the "TF FLASH PROGRAMMING"
window.
In the "Programming Algorithm" group, click the
"Select" button, and select the following Flash
devices:

"AMD 29F040 (512 x 8) 4 Devices"

Set the base address of the Flash to "02800000",
check the "Erase All" radio button.
		
Set the start address of "Available RAM Workspace"
to "00002000" with the "Bytes Of Target RAM Required" set to "6000".

Press the "Erase and Program" button.

Now the Flash memory is programmed with the new boot program.

\sh TrueFFS support


This BSP supports the optional product TrueFFS for Tornado. To use TrueFFS
install the product and define INCLUDE_TFFS in config.h. 

TrueFFS is set up to use the PCMCIA slots and the half of the Flash SIMM that
is not used by the bootrom as drives for use with dosFs.

If you use the function tffsBootImagePut, the "offset parameter should be
computed as (ROM_TEXT_ADRS - ROM_BASE_ADRS) and should evaluate to 0x100 
for the default configuration. The boot-image (i.e. bootrom, bootrom_uncmp
etc) should be filtered using objcopyppc and converted to binary prior to 
using tffsBootImagePut.




DEVICES


The chip drivers included are:
    ppc860Timer.c - Timer library for PPC decrementer, CPM timers 2,3,4
    ppc860Sio.o	  - Serial Communications library for SMC UART
    ppc860Intr.c  - Programmable Interrupt Controller Library
    motFecEnd.o	  - END-style Fast-Ethernet Controller Communication library



The timer driver, ppc860Timer, implements a system clock using the PPC
decrementer timer, an auxiliary clock using CPM timer 2, and a 32-bit
timestamp facilty by cascading CPM timers 3 & 4. The BSP configures SMC1 
as a UART to implement a console device and the CPM SCC1 as an ethernet 
port. 
Fast Ethernet Controller (FEC) makes available fast Ethernet connectivity 
through the use of a MII-compliant physical device and a RJ45 connector.
The FEC will be used as the default network interface. Each time config.h is edited, new vxWorks and bootrom images should be built and Flash memory is to be programmed.



SPECIAL CONSIDERATIONS


The DRAM controller setup is only performed by the boot program. VxWorks
doesn't re-initialize the DRAM controller when it is executed.
The DRAM memory controller initialization is specific for this board only.


The MPC8xx(F)ADS boards do not have a unique Ethernet hardware
address assigned to each board.  A unique address is absolutely necessary if
the user wishes to connect the board to a network.  Thus, the user
must provide a suitable 6 byte Ethernet address for each board used
on a network.  The address is programmed by changing the sysFecEnetAddr
character array in the file sysLib.c.  The first three bytes (0x08, 0x00, 0x3e)
are a Motorola-specific prefix that should be kept as-is.  The user must
change the last three bytes from 0x03, 0x02, 0x01 to three unique bytes
(i.e., bytes not used by any other Motorola Ethernet connection on your net).
Check with your system administrator if you do not know this information.
If these bytes need changing (they often will not), a new boot ROM
must be burned, and a new image must be built.

\sh Known Problems

\ml
\m 1.
A hardware problem causes corruption of some registers and results in 
occasional lockup on boot. This occurs only when the Keep Alive Power source 
is connected to a backup battery. A S/W workaround has been included which 
reduces the possiblity of this problem occuring. It can be included by defining USE_KEY_REGS in config.h.
\m 2.
A problem with the FEC2 MII registers means it must be configured through the
FEC1 interface which means the FEC1 device must be initialised before the 
FEC2 device can be initialised. This order is ensured in configNet.h but to use FEC2 you must use FEC1.
\m 3.
Flash resident vxWorks images require the use of 
INCLUDE_EXC_EXTENDED_VECTOR in config.h to ensure the branch from the 
exception stub can address the flash.
\me

SEE ALSO
\tb VxWorks Programmer's Guide: Getting Started, Configuration