initsru.c

ADI 公司的DSP ADSP21369 EZ-KIT LITE开发板的全部源代码

///////////////////////////////////////////////////////////////////////////////////////
//NAME:     initSRU.c (SPDIF to Analog Talkthrough External PLL)
//DATE:     7/29/05
//PURPOSE:  Talkthrough framework for sending and receiving samples to the AD1835 and SPDIF.
//
//USAGE:    This file initializes the DAI/DPI for accessing the SPDIF Receiver and DACs.
//
////////////////////////////////////////////////////////////////////////////////////////
#include "tt.h"

// The following definition allows the SRU macro to check for errors. Once the routings have
// been verified, this definition can be removed to save some program memory space.
// The preprocessor will issue a warning stating this when using the SRU macro without this
// definition
#define SRUDEBUG  // Check SRU Routings for errors.
#include <SRU.h>

//------------------------------------------------------------------------

void InitSRU(){

// Disable the pull-up resistors on all 20 pins
    *pDAI_PIN_PULLUP = 0x000FFFFF;

//  Tie the pin buffer input LOW.
    SRU(LOW,DAI_PB18_I);

//  Tie the pin buffer enable input LOW
    SRU(LOW,PBEN18_I);

    //  Connect the SPDIF Receiver
    SRU(DAI_PB18_O,DIR_I);

    //  Clock in from SPDIF RX
    SRU(DIR_CLK_O,SPORT0_CLK_I);

    //  Frame sync from SPDIF RX
    SRU(DIR_FS_O,SPORT0_FS_I);

    //  Data in from SPDIF RX
    SRU(DIR_DAT_O,SPORT0_DA_I);

    // Clock on pin 7
    SRU(DIR_CLK_O,DAI_PB07_I);
    // Frame sync on pin 8
    SRU(DIR_FS_O,DAI_PB08_I);
    // Data in on pin 5
    SRU(DAI_PB05_O , SPORT0_DB_I);
    // Tie the pin buffer enable inputs HIGH to drive DAI pins 7 and 8
    SRU(HIGH,PBEN07_I );
    SRU(HIGH,PBEN08_I );

//-----------------------------------------------------------------------------
//
//  Connect the DACs: The codec accepts a BCLK input from DAI pin 13 and
//          a LRCLK (a.k.a. frame sync) from DAI pin 14 and has four
//          serial data outputs to DAI pins 12, 11, 10 and 9
//
//          Connect DAC1 to SPORT1, using data output A
//          Connect DAC2 to SPORT1, using data output B
//          Connect DAC3 to SPORT2, using data output A
//          Connect DAC4 to SPORT2, using data output B
//
//          Connect the clock and frame sync inputs to SPORT1 and SPORT2
//          should come from the SPDIF RX on DAI pins 7 and 8, respectively
//
//          Connect the SPDIF RX BCLK and LRCLK out to the DAC on DAI
//          pins 13 and 14, respectively.
//
//          All six DAC connections are always outputs from the SHARC
//          so tie the pin buffer enable inputs all high.
//

//------------------------------------------------------------------------
//  Connect the pin buffers to the SPORT data lines

    SRU(SPORT2_DB_O,DAI_PB09_I);
    SRU(SPORT2_DA_O,DAI_PB10_I);
    SRU(SPORT1_DB_O,DAI_PB11_I);
    SRU(SPORT1_DA_O,DAI_PB12_I);

//------------------------------------------------------------------------
//  Connect the clock, frame sync from the SPDIF RX directly
//    to the output pins driving the DACs.

    SRU(DIR_CLK_O,DAI_PB13_I);
    SRU(DIR_FS_O,DAI_PB14_I);

//----------------------------------------------------------------------------------
// Connect external APLL (U38) input to SPDIF Rx MCLK output to clean up jitter
// caused by digital PLL in the SPDIF receiver.
//
// Output from external APLL is on DAI Pin 02. Use this to drive audio DAC requiring
// low jitter MCLK.
    SRU(DIR_TDMCLK_O,DAI_PB03_I);
    SRU(DAI_PB02_O,DAI_PB06_I);
    SRU(HIGH,PBEN03_I);
    SRU(LOW,PBEN02_I);

//------------------------------------------------------------------------
//  Connect the SPORT clocks and frame syncs to the clock and
//    frame sync from the SPDIF receiver

    SRU(DIR_CLK_O,SPORT1_CLK_I);
    SRU(DIR_CLK_O,SPORT2_CLK_I);
    SRU(DIR_FS_O,SPORT1_FS_I);
    SRU(DIR_FS_O,SPORT2_FS_I);

//------------------------------------------------------------------------
//  Tie the pin buffer enable inputs HIGH to make DAI pins 6 & 9-14 outputs.
    SRU(HIGH,PBEN06_I);
    SRU(HIGH,PBEN09_I);
    SRU(HIGH,PBEN10_I);
    SRU(HIGH,PBEN11_I);
    SRU(HIGH,PBEN12_I);
    SRU(HIGH,PBEN13_I);
    SRU(HIGH,PBEN14_I);
    //--------------------------------------------------------------------------
// Route SPI signals to AD1835.

    SRU(SPI_MOSI_O,DPI_PB01_I)      //Connect MOSI to DPI PB1.
    SRU(DPI_PB02_O, SPI_MISO_I)     //Connect DPI PB2 to MISO.
    SRU(SPI_CLK_O, DPI_PB03_I)      //Connect SPI CLK to DPI PB3.
    SRU(SPI_FLG3_O, DPI_PB04_I)     //Connect SPI FLAG3 to DPI PB4.
//---------------------------------------------------------------------------
// Tie pin buffer enable from SPI peipherals to determine whether they are
// inputs or outputs

    SRU(SPI_MOSI_PBEN_O, DPI_PBEN01_I);
    SRU(SPI_MISO_PBEN_O, DPI_PBEN02_I);
    SRU(SPI_CLK_PBEN_O, DPI_PBEN03_I);
    SRU(SPI_FLG3_PBEN_O, DPI_PBEN04_I);

//-----------------------------------------------------------------------------

}