post_common.c

ADI 公司的DSP ADSP21369 EZ-KIT LITE开发板的全部源代码

//////////////////////////////////////////////////////////////////////////////
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#ifdef __ADSP21375__
	#include <Cdef21375.h>
	#include <def21375.h>

	#define SDNOBSTOP (BIT_31)	//  def21375.h

#elif __ADSP21369__
	#include <Cdef21369.h>
	#include <def21369.h>
#endif

#include <sru.h>
#include <signal.h>
#include <math.h>
#include <stdlib.h>
#include <filter.h>

#include "post_common.h"



#define SDMODIFY  (BIT_17)
void InitPLL(void)
{
	int n;

#ifdef __ADSP21369__

	if( (0 == __SILICON_REVISION__) || (0xFFFF == __SILICON_REVISION__) )
	{	// 333 Mhz
		//*pPMCTL = (PLLM27|PLLD2|DIVEN);

		// rev ezkit board REV is less than 1.2, run SDRAM at 133Mhz vs. 166Mhz.
		*pPMCTL = (PLLM27 | PLLD2 | DIVEN | SDCKR2_5);
	}
	else
	{
		// CLKIN= 24.576.5 MHz, Multiplier= 16, Divisor= 1, CCLK_SDCLK_RATIO 2.5.
		// Core clock = (24.576MHz * 16) /1 = 393.216 MHz
		// rev ezkit board REV is less than 1.2, run SDRAM at 133Mhz vs. 166Mhz.
    	*pPMCTL = (PLLM16 | PLLD1 | DIVEN | SDCKR2_5);
	}

#elif __ADSP21375__
//	//Core clock = (16.384MHz * 16) /1 = 262.144 MHz run SDRAM at 133
	*pPMCTL = (PLLM32 | PLLD2 | DIVEN | SDCKR2);   // Input divider | PLL Multiplier 48;
#endif

    n = *pPMCTL;
    n |= PLLBP;
    n  ^= DIVEN;
    *pPMCTL = n;

     // Wait at least 4096 cycles for the pll to lock
    for(n = 0; n < 5000; n++ )
    {
    	asm("nop;");
    }

    *pPMCTL ^= PLLBP;


#ifdef __ADSP21369__
    // Programming SDRAM control registers.
    // RDIV = ((f SDCLK X t REF )/NRA) - (tRAS + tRP )
    //===================================================================
    //
    // Configure SDRAM Control Register (SDCTL) for the Micron MT48LC4M32
    //
    //  SDCL3  : SDRAM CAS Latency= 3 cycles
    //  DSDCLK1: Disable SDRAM Clock 1
    //  SDPSS  : Start SDRAM Power up Sequence
    //  SDCAW8 : SDRAM Bank Column Address Width= 8 bits
    //  SDRAW12: SDRAM Row Address Width= 12 bits
    //  SDTRAS7: SDRAM tRAS Specification. Active Command delay = 7 cycles
    //  SDTRP3 : SDRAM tRP Specification. Precharge delay = 3 cycles.
    //  SDTWR2 : SDRAM tWR Specification. tWR = 2 cycles.
    //  SDTRCD3: SDRAM tRCD Specification. tRCD = 3 cycles.
    //
    //--------------------------------------------------------------------
	*pSDCTL = (SDCL3|DSDCLK1|SDPSS|SDCAW8|SDRAW12|SDTRAS7|SDTRP3|SDTWR2|SDTRCD3);


    // CCLK_SDCLK_RATIO==25
    // (160*(10^6)*64*(10^-3)/4096) - (7+3) = 2490
	*pSDRRC = (SDMODIFY|SDROPT | 0x9BA);// Enabling SDRAM read optimization

    // Note that MS2 & MS3 pin multiplexed with flag2 & flag3.
    // MSEN bit must be enabled to access SDRAM, but LED8 cannot be driven with sdram
    // Note that MS2 & MS3 pin multiplexed with flag2 & flag3
    // Programming the mutliplexed pin as MS2
    *pSYSCTL |= MSEN;

    // Mapping Bank 2 to SDRAM
    // Make sure that jumper is set appropriately so that MS2 is connected to
    // chip select of 16-bit SDRAM device
    *pEPCTL |= B2SD;

#elif __ADSP21375__
    // Programming SDRAM control registers.
    // RDIV = ((f SDCLK X t REF )/NRA) - (tRAS + tRP )
    //===================================================================
    //
    // Configure SDRAM Control Register (SDCTL) for the
    //
    //  SDNOBSTOP : Disable burst-mode on SDRAM
    //  SDCL3  : SDRAM CAS Latency= 3 cycles
    //  DSDCLK1: Disable SDRAM Clock 1
    //  SDPSS  : Start SDRAM Power up Sequence
    //  SDCAW9 : SDRAM Bank Column Address Width= 9 bits
    //  SDRAW12: SDRAM Row Address Width= 12 bits
    //  SDTRAS6: SDRAM tRAS Specification. Active Command delay = 6 cycles
    //  SDTRP3 : SDRAM tRP Specification. Precharge delay = 3 cycles.
    //  SDTWR2 : SDRAM tWR Specification. tWR = 2 cycles.
    //  SDTRCD3: SDRAM tRCD Specification. tRCD = 3 cycles.
    //  X16DE  : Enable external SDRAM bus width to be 16-bits wide
    //
    //--------------------------------------------------------------------

    *pSDCTL = SDNOBSTOP|SDCL3|DSDCLK1|SDPSS|SDCAW9|SDRAW12|SDTRAS6|SDTRP3|SDTWR2|SDTRCD3|X16DE;





    // CCLK_SDCLK_RATIO==2
	*pSDRRC = 0x307FC;

    // Programming the mutliplexed pin as MS0
    *pSYSCTL |= MSEN;

    // Mapping Bank 0 to SDRAM
    *pEPCTL |= B0SD;
#endif



    //===================================================================
    //
    // Configure AMI Control Register (AMICTL0) Bank 0 for the ISSI IS61LV5128
    //
    //  WS2 : Wait States= 2 cycles
    //  HC1  : Bus Hold Cycle (at end of write access)= 1 cycle.
    //  AMIEN: Enable AMI
    //  BW8  : External Data Bus Width= 8 bits.
    //
    //--------------------------------------------------------------------
#if ( defined(__ADSP21375__) || defined(__ADSP21369__) )
	*pEPCTL = (((*pEPCTL) & (~B0SD)) | EPBRCORE);
#endif

	*pAMICTL0 = ((*pAMICTL0) & ((~HC1) | (~HC2) | (~RHC1) | ~(RHC2) | (~PKDIS) | (~MSWF) | (~BW16) | (~BW32) | (~PREDIS)) | (WS4 | IC7 | AMIEN | AMIFLSH));

    //===================================================================
    //
    // Configure AMI Control Register (AMICTL) Bank 1 for the AMD AM29LV08
    //
    //  WS23 : Wait States= 23 cycles
    //  AMIEN: Enable AMI
    //  BW8  : External Data Bus Width= 8 bits.
    //
    //--------------------------------------------------------------------


	// setup EPCTL to use bank 2 (MS1) core accesses.
#if ( defined(__ADSP21375__) || defined(__ADSP21369__) )
	*pEPCTL = (((*pEPCTL) & (~B1SD)) | EPBRCORE);
#endif

	// NOTE:  The PKDIS bit is set which makes a 1 to 1 mapping, each 8 bit byte
	///       maps to an address.
	*pAMICTL1 = ( PKDIS | WS31 | HC1 | HC2 | RHC1 | RHC2 | IC7 | AMIEN | AMIFLSH);


/*	int n;

	//
	// init the PLL
	//
	*pPMCTL = (PMCTL_SETTING | PMCTL_SDRAM_SETTING);

     // Wait for around 4096 cycles for the pll to lock
    for(n = 0; n < 5000; n++ )
    {
    	asm("nop;");
    }

    *pPMCTL &= (~PLLBP);

    // init the SDRAM
	*pSDCTL = SDCTL_SETTING;
	*pSDRRC = (SDRRC_SETTING | SDMODIFY | SDROPT);
*/
}


void Delay(const int iVal)
{
	int nDelay;
	for( nDelay = 0; nDelay < iVal; nDelay++)
	{
		asm("nop;");
	}
}


void Config_SRU_DAI(void)
{

//-----------------------------------------------------------------------------
//
//  MCLK: The output of the 12.288 MHz xtal is either directly connected to the
//          codec, but also connected to DAI_P06, or just to DAI_P17. This is
//             determined by switches 7.1 and 7.2 For this example we route the
//             MCLK into DAI_P17 and supply the clock to the ADC via DAI_P06
//             by routing the signal through the SRU.

    SRU(LOW,DAI_PB17_I);	//  Tie the pin buffer input LOW.
    SRU(LOW,PBEN17_I);		//  Tie the pin buffer enable input LOW

///
/// external PLL stuff
///
    SRU(LOW,DAI_PB02_I);		//  Tie the pin buffer input LOW.
    SRU(LOW,PBEN02_I);			//  Tie the pin buffer enable input LOW
    SRU(HIGH,PBEN17_I);			//  Tie the pin buffer enable input LOW
    SRU(DAI_PB17_O,DAI_PB03_I);	//  Route the MCLK through the External Analog PLL
    SRU(DAI_PB02_O,DAI_PB06_I);	//  Route the MCLK from the External Analog PLL to the 1835


//-----------------------------------------------------------------------------
//
//  Connect the ADC: The codec drives a BCLK output to DAI pin 7, a LRCLK
//          (a.k.a. frame sync) to DAI pin 8 and data to DAI pin 5.
//
//          Connect the ADC to SPORT0, using data input A
//
//          All three lines are always inputs to the SHARC so tie the pin
//          buffer inputs and pin buffer enable inputs all low.


//------------------------------------------------------------------------
//  Connect the ADC to SPORT0, using data input A

    //  Clock in on pin 7
    SRU(DAI_PB07_O,SPORT0_CLK_I);

    //  Frame sync in on pin 8
    SRU(DAI_PB08_O,SPORT0_FS_I);

    //  Data in on pin 5
    SRU(DAI_PB05_O,SPORT0_DA_I);

//------------------------------------------------------------------------
//  Tie the pin buffer inputs LOW for DAI pins 5, 6 7 and 8.  Even though
//    these pins are inputs to the SHARC, tying unused pin buffer inputs
//    LOW is "good coding style" to eliminate the possibility of
//    termination artifacts internal to the IC.  Note that signal
//    integrity is degraded only with a few specific SRU combinations.
//    In practice, this occurs VERY rarely, and these connections are
//    typically unnecessary.


    SRU(LOW,DAI_PB05_I);
    SRU(LOW,DAI_PB07_I);
    SRU(LOW,DAI_PB08_I);

//------------------------------------------------------------------------
//  Tie the pin buffer enable inputs LOW for DAI pins 5, 6, 7 and 8 so
//    that they are always input pins.

    SRU(LOW,PBEN05_I);
    SRU(LOW,PBEN07_I);
    SRU(LOW,PBEN08_I);

//-----------------------------------------------------------------------------
//
//  Connect the DACs: The codec accepts a BCLK input from DAI pin 13 and
//          a LRCLK (a.k.a. frame sync) from DAI pin 14 and has four
//          serial data outputs to DAI pins 12, 11, 10 and 9