initpll_sdram.asm

ADI 公司的DSP ADSP21369 EZ-KIT LITE开发板的全部源代码

/* Sets up the SDRAM controller to access SDRAM. In this file are two subroutines, the first
   to set up the SHARC's PLL, and the second to set up the SDRAM controller.
   CLKIN= 24.576 MHz, Multiplier= 27, Divisor= 2, CCLK_SDCLK_RATIO 2.0.
   Core clock = (24.576MHz * 27) /2 = 331.776 MHz
*/

#include <def21369.h>

.global _initPLL;
.global _initSDRAM;

.section/pm seg_pmco;

_initPLL:

// CLKIN= 24.576 MHz, Multiplier= 27, Divisor= 2, CCLK_SDCLK_RATIO 2.
// Core clock = (24.576MHz * 27) /2 = 331.776 MHz
    ustat3 = PLLM27|PLLD2|DIVEN;

changePLL:

    // Set the Core clock (CCLK) to SDRAM clock (SDCLK) ratio to 2
   bit set ustat3 SDCKR2;

    dm(PMCTL) = ustat3;
    bit set ustat3 PLLBP;

    dm(PMCTL) = ustat3;

     // Wait for at least 4096 cycles for the pll to lock
    lcntr = 5000, do loopend2 until lce;
loopend2:     nop;

    ustat3 = dm(PMCTL);
    bit clr ustat3 PLLBP;
    dm(PMCTL) = ustat3;

_initPLL.end: rts;


_initSDRAM:

    // Programming SDRAM control registers.
    // RDIV = ((f SDCLK X t REF )/NRA) - (tRAS + tRP )

    // CCLK_SDCLK_RATIO==2
    ustat4 = 0xA17; // (166*(10^6)*64*(10^-3)/4096) - (7+3) = 2583


    //===================================================================
    //
    // Configure SDRAM Control Register (SDCTL) for the Micron MT48LC4M32
    //
    //  SDCL3  : SDRAM CAS Latency= 3 cycles
    //  DSDCLK1: Disable SDRAM Clock 1
    //  SDPSS  : Start SDRAM Power up Sequence
    //  SDCAW8 : SDRAM Bank Column Address Width= 8 bits
    //  SDRAW12: SDRAM Row Address Width= 12 bits
    //  SDTRAS7: SDRAM tRAS Specification. Active Command delay = 7 cycles
    //  SDTRP3 : SDRAM tRP Specification. Precharge delay = 3 cycles.
    //  SDTWR2 : SDRAM tWR Specification. tWR = 2 cycles.
    //  SDTRCD3: SDRAM tRCD Specification. tRCD = 3 cycles.
    //
    //--------------------------------------------------------------------

    ustat3 = SDCL3|DSDCLK1|SDPSS|SDCAW8|SDRAW12|SDTRAS7|SDTRP3|SDTWR2|SDTRCD3;

    dm(SDCTL) = ustat3;

    // Change this value to optimize the performance for quazi-sequential accesses (step > 1)
    #define SDMODIFY 1                    // Setting the Modify to 1
    bit set ustat4 (SDMODIFY<<17)|SDROPT; // Enabling SDRAM read optimization

    dm(SDRRC) = ustat4;

    // Note that MS2 & MS3 pin multiplexed with flag2 & flag3.
    // MSEN bit must be enabled to access SDRAM, but LED8 cannot be driven with sdram
    ustat3=dm(SYSCTL);
    bit set ustat3 MSEN;    //This setting allows SDRAM access
    //bit clr ustat3 MSEN;  //This setting allows Flag3 to be used
    dm(SYSCTL)=ustat3;

    // Mapping Bank 2 to SDRAM
    // Make sure that jumper is set appropriately so that MS2 is connected to
    // chip select of 16-bit SDRAM device
    ustat3 = dm(EPCTL);
    bit set ustat3 B2SD;
    bit clr ustat3 B0SD|B1SD|B3SD;
    dm(EPCTL) = ustat3;

    //===================================================================
    //
    // Configure AMI Control Register (AMICTL0) Bank 0 for the ISSI IS61LV5128
    //
    //  WS2 : Wait States= 2 cycles
    //  HC1  : Bus Hold Cycle (at end of write access)= 1 cycle.
    //  AMIEN: Enable AMI
    //  BW8  : External Data Bus Width= 8 bits.
    //
    //--------------------------------------------------------------------

    //SRAM Settings
    ustat4 = WS2|HC1|AMIEN|BW8;
    dm(AMICTL0)= ustat4;

    //===================================================================
    //
    // Configure AMI Control Register (AMICTL) Bank 1 for the AMD AM29LV08
    //
    //  WS23 : Wait States= 23 cycles
    //  AMIEN: Enable AMI
    //  BW8  : External Data Bus Width= 8 bits.
    //
    //--------------------------------------------------------------------

    //Flash Settings
    ustat4 = WS23|AMIEN|BW8;
    dm(AMICTL1)= ustat4;


_initSDRAM.end: rts;