sport dma driven.c

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

// **********************************************************************************
// *  ADSP-2126x SPORT Internal Loopback Example - DMA Driven Example        *
// *                                                                                *
// *  This example loops back data from tx_buf to rx_buf via SPORT4 to SPORT5       *
// *                                                                                *
// *                                                                                *
// *  Author: Brian M.                                                        *
// *  Analog Devices, Inc.                                                          *
// *  Rev 1.0                                                                       *
// *  7/03                                                                        *
// **********************************************************************************

#include <signal.h>
#define bufsize 10

// Interrupt Control Bits
#define IRPTEN  0x00001000
#define SP5I    0x00010000
#define SP4IMSK 0x00001000
#define SP4I    0x00000004

// SPORT DMA Parameter Registers
#define IISP4A  0x840
#define IISP5A  0x848
#define IMSP4A  0x841
#define IMSP5A  0x849
#define CSP4A   0x842
#define CSP5A   0x84A

// SPORT Control Registers
#define DIV4    0x802
#define DIV5    0x803
#define SPCTL4  0x800
#define SPCTL5  0x801
#define SPMCTL45 0x804

// SPORT Control Bits
#define SPL     0x00001000
#define SPEN_A  0x00000001
#define SDEN_A  0x00040000
#define SLEN32  0x000001F0
#define SPTRAN  0x02000000
#define IFS     0x00004000
#define FSR     0x00002000
#define ICLK    0x00000400

void Count_SPORT4_RX_IRQs(int);
void Count_SPORT5_TX_IRQs(int);



int tx_buf5a[bufsize]= {0x11111111,
                        0x22222222,
                        0x33333333,
                        0x44444444,
                        0x55555555,
                        0x66666666,
                        0x77777777,
                        0x88888888,
                        0x99999999,
                        0xAAAAAAAA};
int rx_buf4a[bufsize];

/* ISR counters, for debug purposes to see how many times SPORT DMA interrupts are serviced */
int SP4I_counter = 0;
int SP5I_counter = 0;

void main()
{
    interrupt(SIG_SP4,Count_SPORT4_RX_IRQs);
    interrupt(SIG_SP5,Count_SPORT5_TX_IRQs);


/////////////////////////////////////////////////////////////////////////////////////////
//                                                                                     //
//              SPORT Loopback init/test: Use SPORT4 as RX & SPORT5 as TX              //
//                                                                                     //
/////////////////////////////////////////////////////////////////////////////////////////

        // initially clear SPORT control register
        * (volatile int *) SPCTL4 = 0;
        * (volatile int *) SPCTL5 = 0;
        * (volatile int *) SPMCTL45 = 0;

SPORT_DMA_setup:
        * (volatile int *) IISP5A = (int) tx_buf5a;    /* Internal DMA memory address                   */
        * (volatile int *) IMSP5A = 1;  /* Internal DMA memory access modifier          */
        * (volatile int *) CSP5A = sizeof(tx_buf5a);        /* Contains number of DMA transfers to be done */

        * (volatile int *) IISP4A = (int) rx_buf4a; /* Internal DMA memory address                  */
        * (volatile int *) IMSP4A = 1;  /* Internal DMA memory access modifier          */
        * (volatile int *) CSP4A = sizeof(rx_buf4a);        /* Contains number of DMA transfers to be done */

        /* set internal loopback bit for SPORT4 & SPORT5 */
        * (volatile int *) SPMCTL45 |= SPL;

        /* Configure SPORT5 as a transmitter */
        /* CLKDIV3=[fCCLK(200 MHz)/2xFSCLK(20 MHz)]-1 = 0x0004 */
        /* FSDIV3=[FSCLK(20 MHz)/TFS(.625 MHz)]-1 = 31 = 0x001F */
        * (volatile int *) DIV5 = 0x001F0004;   //internally generating clock and frame sync
        * (volatile int *)  SPCTL5 = (SPEN_A | SLEN32 | FSR | SPTRAN | SDEN_A | IFS | ICLK);

        /* Configure SPORT4 as a reciever */
        * (volatile int *) DIV4 = 0;        /* externally generating clock and frame sync */
        * (volatile int *) SPCTL4 = (SPEN_A | SLEN32 | FSR | SDEN_A);


        for(;;)
        {}

}
/////////////////////////////////////////////////////////////
//                                                         //
//     SPORT4 and SPORT5 Interrupt Service Routines        //
//                                                         //
/////////////////////////////////////////////////////////////

void Count_SPORT4_RX_IRQs(int sig_int)
{
    SP4I_counter++;             /* increment count */
}

void Count_SPORT5_TX_IRQs(int sig_int)
{
    SP5I_counter++;                 /* increment count */
}