parallel port dma driven.asm

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

/* Register Definitions */
#define PPCTL       0x1800
#define EIPP        0x1810
#define EMPP        0x1811
#define ECPP        0x1812
#define IIPP        0x1818
#define IMPP        0x1819
#define ICPP        0x181a

/* Register Bit Definitions */
#define PPEN    0x00000001
#define PPDUR20 0x00000026
#define PPBHC   0x00000040
#define PP16    0x00000080
#define PPDEN   0x00000100
#define PPTRAN  0x00000200
#define PPBS    0x00020000

/* Source Buffer */
.section/dm seg_dmda;
.var source[8] = 0x11111111,
                 0x22222222,
                 0x33333333,
                 0x44444444,
                 0x55555555,
                 0x66666666,
                 0x77777777,
                 0x88888888;

.global _main;
.section/pm seg_pmco;
_main:
ustat3=dm(PPCTL);       /*disable parallel port*/
bit clr ustat3 PPEN|PPDEN;
dm(PPCTL)=ustat3;

/* initiate parallel port DMA registers*/
r0=source;          dm(IIPP)=r0;
r0=1;               dm(IMPP)=r0;
r0=LENGTH(source);  dm(ICPP)=r0;

r0=1;               dm(EMPP)=r0;
r0=0x1000000;       dm(EIPP)=r0;
/* For 16-bit external memory, the External count is
    double the internal count */
r0=LENGTH(source) * 2;      dm(ECPP)=r0;

ustat3=  PP16|      /*for a 16-bit external memory */
         PPTRAN|    /* transmit (write) */
         PPBHC|     /* implement a bus hold cycle*/
         PPDUR20;   /* make pp data cycles last for a */
                    /* duration of 20 cclk cycles */
dm(PPCTL)=ustat3;

/* initiate PP DMA*/
/*Enable Parallel Port and PP DMA in same cycle*/
ustat4=dm(PPCTL);
bit set ustat4 PPDEN|PPEN;
dm(PPCTL)=ustat4;

_main.end: jump(pc,0);