sport dma driven.asm

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

/* SPORT DMA Parameter Registers */
#define IISP4A  0x840
#define IISP5A  0x848
#define IMSP4A  0x841
#define IMSP5A  0x849
#define CSP4A   0x842
#define CSP5A   0x84A

/* SPORT Control Registers */
#define DIV4    0x802
#define DIV5    0x803
#define SPCTL4  0x800
#define SPCTL5  0x801
#define SPMCTL45 0x804

/* SPMCTL Bits */
#define SPL     0x00001000

/* SPCTL Bits */
#define SPEN_A  0x00000001
#define SDEN_A  0x00040000
#define SLEN32  0x000001F0
#define SPTRAN  0x02000000
#define IFS     0x00004000
#define FSR     0x00002000
#define ICLK    0x00000400

/* Default Buffer Length */
#define BUFSIZE 10

.SECTION/DM seg_dmda;
/*Transmit buffer*/
.var tx_buf5a[BUFSIZE]= 0x11111111,
                        0x22222222,
                        0x33333333,
                        0x44444444,
                        0x55555555,
                        0x66666666,
                        0x77777777,
                        0x88888888,
                        0x99999999,
                        0xAAAAAAAA;

/*Receive buffer*/
.var rx_buf4a[BUFSIZE];

/* Main code section */
.global _main;
.SECTION/PM seg_pmco;
_main:
/*//////////////////////////////////////////////////////////
//                                                        //
//   SPORT Loopback: Use SPORT4 as RX & SPORT5 as TX      //
//                                                        //
//////////////////////////////////////////////////////////*/
/* initially clear SPORT control register */
r0=0x00000000;
dm(SPCTL4)=r0;
dm(SPCTL5)=r0;
dm(SPMCTL45)=r0;

SPORT_DMA_setup:
/* SPORT 5 Internal DMA memory address */
r0=tx_buf5a;    dm(IISP5A)=r0;
/* SPORT 5 Internal DMA memory access modifier  */
r0=1;           dm(IMSP5A)=r0;
/* SPORT 5 Number of DMA transfers to be done */
r0=@tx_buf5a;   dm(CSP5A)=r0;

/* SPORT 4 Internal DMA memory address */
r0=rx_buf4a;    dm(IISP4A)=r0;
/* SPORT 4 Internal DMA memory access modifier */
r0=1;           dm(IMSP4A)=r0;
/* SPORT 4 Number of DMA5 transfers to be done */
r0=@rx_buf4a;   dm(CSP4A)=r0;

/* set internal loopback bit for SPORT4 & SPORT5 */
bit set ustat3 SPL;
dm(SPMCTL45) = ustat3;

/* Configure SPORT5 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV=[fCCLK(200 MHz)/2xFSCLK(20 MHz)]-1 = 0x0004 */
/* FSDIV=[FSCLK(20 MHz)/TFS(.625 MHz)]-1 = 31 = 0x001F */
R0 = 0x001F0004;    dm(DIV5) = R0;
ustat4 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR|       /* Frame Sync Required */
         SPTRAN|    /* Transmit on enabled channels */
         SDEN_A|    /* Enable Channel A DMA */
         IFS|       /* Internally Generated Frame Sync */
         ICLK;      /* Internally Generated Clock */
dm(SPCTL5) = ustat4;

/* Configure SPORT4 as a reciever */
/* externally generating clock and frame sync */
r0=0x0;     dm(DIV4) = R0;
ustat3 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR|       /* Frame Sync Required */
         SDEN_A;    /* Enable Channel A DMA */
dm(SPCTL4) = ustat3;

_main.end:  jump (pc,0);