initdai.c

来自「ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代」· C语言 代码 · 共 134 行

///////////////////////////////////////////////////////////////////////////////////////
//NAME:     initDAI.c (Block-based Talkthrough)
//DATE:     8/5/2005
//PURPOSE:  Talkthrough framework for sending and receiving samples to the AD1835.
//
//USAGE:    This file initializes the DAI for accessing the ADC and DACs.
//
//LAST UPDATE: 08-05-2005 Added SRU Error Check
////////////////////////////////////////////////////////////////////////////////////////
#include "tt.h"
// The following definition allows the SRU macro to check for errors. Once the routings have
// been verified, this definition can be removed to save some program memory space.
// The preprocessor will issue a warning stating this when using the SRU macro without this
// definition
#define SRUDEBUG  // Check SRU Routings for errors.
#include <SRU.h>

//------------------------------------------------------------------------

void InitDAI(){



//========================================================================
//
//  MCLK: Route the MCLK recovered from the SPDIF receiver to the ADC
//
    SRU(DAI_PB02_O, DAI_PB06_I);
    SRU(LOW,DAI_PB02_I);
    SRU(LOW,PBEN02_I );

    SRU(HIGH,PBEN06_I );


//========================================================================
//
//  Connect the SPDIF: The CS8416 drives a BCLK output into DAI pin 7, a
//          LRCLK (a.k.a. frame sync) into DAI pin 8 and data into DAI pin 5.
//
//          Connect the SPDIF to SPORT0, using data input A
//
//          All three lines are always inputs to the SHARC so tie the pin
//          buffer inputs and pin buffer enable inputs all low.
//------------------------------------------------------------------------

//  Connect the SPDIF receiver to SPORT0, using data input A
    SRU(DAI_PB03_O , SPORT0_CLK_I);
    SRU(DAI_PB04_O , SPORT0_FS_I );
    SRU(DAI_PB01_O , SPORT0_DA_I );

//------------------------------------------------------------------------
//  Tie the pin buffer inputs LOW for DAI pins 1, 3 and 4
    SRU(LOW,DAI_PB01_I);
    SRU(LOW,DAI_PB03_I);
    SRU(LOW,DAI_PB04_I);

//------------------------------------------------------------------------
//  Tie the pin buffer enable inputs LOW for DAI pins 1, 3 and 4
    SRU(LOW,PBEN01_I );
    SRU(LOW,PBEN03_I );
    SRU(LOW,PBEN04_I );

//------------------------------------------------------------------------
//  Use DAI pin 15 as an SPI device select line for the SPDIF
    SRU(HIGH,DAI_PB15_I);
    SRU(HIGH,PBEN15_I );

//------------------------------------------------------------------------
//  Define the SPDIF "non-audio" signal line as an input
    SRU(LOW,PBEN16_I );






//========================================================================
//
//  Connect the DACs: The codec accepts a BCLK input from DAI pin 13 and
//          a LRCLK (a.k.a. frame sync) from DAI pin 14 and has four
//          serial data outputs to DAI pins 12, 11, 10 and 9
//
//          Connect DAC1 to SPORT1, using data output A
//          Connect DAC2 to SPORT1, using data output B
//          Connect DAC3 to SPORT2, using data output A
//          Connect DAC4 to SPORT2, using data output B
//
//          Connect the clock and frame sync inputs to SPORT1 and SPORT2
//          should come from the SPDIF on DAI pins 7 and 8, respectively
//
//          Connect the SPDIF BCLK and LRCLK back out to the DAC on DAI
//          pins 13 and 14, respectively.
//
//          All six DAC connections are always outputs from the SHARC
//          so tie the pin buffer enable inputs all high.
//
//------------------------------------------------------------------------
//  Connect the pin buffers to the SPORT data lines and ADC BCLK & LRCLK

    SRU(DAI_PB03_O , SPORT1_CLK_I);//from SPDIF
    SRU(DAI_PB04_O , SPORT1_FS_I); //from SPDIF

    SRU(SPORT1_DA_O, DAI_PB12_I);  //to DAC1
    SRU(HIGH, PBEN12_I); //enable S1DA output on pin 12

    SRU(SPORT1_DB_O, DAI_PB11_I);  //to DAC2
    SRU(HIGH, PBEN11_I); //enable S1Db output on pin 11


    SRU(DAI_PB03_O , SPORT2_CLK_I);//from SPDIF
    SRU(DAI_PB04_O , SPORT2_FS_I); //from SPDIF

    SRU(SPORT2_DA_O, DAI_PB10_I);  //to DAC3
    SRU(HIGH, PBEN10_I); //enable S2Da output on pin 10

    SRU(SPORT2_DB_O, DAI_PB09_I);  //to DAC4
    SRU(HIGH, PBEN09_I); //enable S2Db output on pin 9


    SRU(DAI_PB03_O , DAI_PB13_I); //clock (BCLK) input from SPDIF on PB03 fed back to DAC via PB13
    SRU(HIGH, PBEN13_I); //enable BCLK to DACs

    SRU(DAI_PB04_O , DAI_PB14_I); //FS (LRCLK) input from SPDIF on PB04 fed back to DAC via PB14
    SRU(HIGH, PBEN14_I); //enable LRCLK to DACs



}