programmable clock generator external input clock.c

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

//Register Definitions
#define SRU_CLK3    0x2434
#define SRU_PIN0    0x2460
#define SRU_PBEN0   0x2478
#define PCG_CTLA0   0x24C0
#define PCG_CTLA1   0x24C1
#define PCG_CTLB0   0x24C2
#define PCG_CTLB1   0x24C3
#define PCG_PW      0x24C4

//SRU Definitions
#define PCG_CLKA_O      0x1c
#define PCG_CLKB_P      0x39
#define PCG_FSB_P       0x3B
#define PBEN_HIGH_Of    0x01

//Bit Positions
#define PCG_EXTB_I      5
#define DAI_PB02        6
#define PCG_PWB         16

//Bit Definitions
#define ENCLKA      0x80000000
#define ENFSB       0x40000000
#define ENCLKB      0x80000000
#define CLKBSOURCE  0x80000000
#define FSBSOURCE   0x40000000

void main()
{
    * (volatile int *) SRU_CLK3 = (PCG_CLKA_O<<PCG_EXTB_I); //Route PCG Clock A Output to PCG_EXTB_I via SRU

    * (volatile int *) PCG_CTLA0 = ENCLKA;  //FS Divisor = 0 & FS Phase 10-19 =0, Enable Clock

    * (volatile int *) PCG_CTLA1 = 0xfffff;  //CLK Divisor = 0xFFFFF & FS Phase 0-9 =0, Use CLKIN as source

    * (volatile int *) SRU_PIN0 = (PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02)); //Route PCG Clock B Output to DAI Pin 1
																	  //Route PCG FS B Output to DAI Pin 2
																	  
    * (volatile int *) SRU_PBEN0 = (PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02)); //Enable DAI Pins 1&2 as outputs

    * (volatile int *) PCG_PW = (5<<PCG_PWB);  //PCG Channel B pulse width = 5

    * (volatile int *) PCG_CTLB0 = (ENFSB|ENCLKB|10);  //FS Divisor = 0 & FS Phase 10-19 =0, Enable Clock and FS

    * (volatile int *) PCG_CTLB1 = (CLKBSOURCE|FSBSOURCE|10);  //CLK Divisor = 0xFFFFF & FS Phase 0-9 = 0,
    														   //Use PCG_EXTB_I as source

    for(;;)
    {}
}