sport dma chaining.asm

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

/* SPORT DMA Parameter Registers */
#define CPSP0A  0xC43
#define CPSP1A  0xC4B

/* SPORT Control Registers */
#define DIV0    0xC02
#define DIV1    0xC03
#define SPCTL0  0xC00
#define SPCTL1  0xC01
#define SPMCTL01 0xC04

/* SPMCTL Bits */
#define SPL     0x00001000

/* SPCTL Bits */
#define SPEN_A  0x00000001
#define SDEN_A  0x00040000
#define SCHEN_A 0x00080000
#define SLEN32  0x000001F0
#define SPTRAN  0x02000000
#define IFS     0x00004000
#define FSR     0x00002000
#define ICLK    0x00000400

/* Default Buffer Length */
#define BUFSIZE 10

.SECTION/DM seg_dmda;
/* TX Buffers */
.var tx_buf1a[BUFSIZE]= 0x11111111,
                        0x22222222,
                        0x33333333,
                        0x44444444,
                        0x55555555,
                        0x66666666,
                        0x77777777,
                        0x88888888,
                        0x99999999,
                        0xAAAAAAAA;

.var tx_buf1b[BUFSIZE]= 0x12345678,
                        0x23456789,
                        0x3456789A,
                        0x456789AB,
                        0x56789ABC,
                        0x6789ABCD,
                        0x789ABCDE,
                        0x89ABCDEF,
                        0x9ABCDEF0,
                        0xABCDEF01;
/* RX Buffers */
.var rx_buf0a[BUFSIZE];
.var rx_buf0b[BUFSIZE];

/* TX Transfer Control Blocks */
.var tx_tcb1[4]=0,BUFSIZE,1,tx_buf1a;
.var tx_tcb2[4]=0,BUFSIZE,1,tx_buf1b;

/* RX Transfer Control Blocks */
.var rx_tcb1[4]=0,BUFSIZE,1,rx_buf0a;
.var rx_tcb2[4]=0,BUFSIZE,1,rx_buf0b;

/* Main code section */
.global _main;
.SECTION/PM seg_pmco;
_main:
/*//////////////////////////////////////////////////////////
//                                                        //
//     SPORT Loopback: Use SPORT0 as RX & SPORT1 as TX    //
//                                                        //
//////////////////////////////////////////////////////////*/
/* initially clear SPORT control register */
r0=0x00000000;
dm(SPCTL0)=r0;
dm(SPCTL1)=r0;
dm(SPMCTL01)=r0;

SPORT_DMA_setup:
/* set internal loopback bit for SPORT0 & SPORT1 */
bit set ustat3 SPL;
dm(SPMCTL01) = ustat3;

/* Configure SPORT1 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV3=[fCCLK(200 MHz)/2xFSCLK(20 MHz)]-1 = 0x0004 */
/* FSDIV3=[FSCLK(20 MHz)/TFS(.625 MHz)]-1 = 31 = 0x001F */
R0 = 0x001F0004;    dm(DIV1) = R0;
ustat4 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR|       /* Frame Sync Required */
         SPTRAN|    /* Transmit on enabled channels */
         SDEN_A|    /* Enable Channel A DMA */
         SCHEN_A|   /* Enable Channel A DMA Chaining */
         IFS|       /* Internally Generated Frame Sync */
         ICLK;      /* Internally Generated Clock */
dm(SPCTL1) = ustat4;

/* Configure SPORT0 as a reciever */
/* externally generating clock and frame sync */
r0=0x0;     dm(DIV0) = R0;
ustat3 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR|       /* Frame Sync Required */
         SDEN_A|    /* Enable Channel A DMA */
         SCHEN_A;   /* Enable Channel A DMA Chaining */
dm(SPCTL0) = ustat3;

/* Next TCB location for tx_tcb2 is tx_tcb1 */
/* Mask the first 19 bits of the TCB location */
r0=(tx_tcb1+3)&0x7FFFF;
dm(tx_tcb2)=r0;

/* Next TCB location for rx_tcb2 is rx_tcb1 */
/* Mask the first 19 bits of the TCB location */
r0=(rx_tcb1+3)&0x7FFFF;
dm(rx_tcb2)=r0;

/* Next TCB location for rx_tcb1 is rx_tcb2 */
/* Mask the first 19 bits of the TCB location */
r0=(rx_tcb2+3)&0x7FFFF;
dm(rx_tcb1)=r0;
/* Initialize SPORT DMA transfer by writing to the CP reg */
dm(CPSP0A)=r0;

/* Next TCB location for tx_tcb1 is tx_tcb2 */
/* Mask the first 19 bits of the TCB location */
r0=(tx_tcb2+3)&0x7FFFF;
dm(tx_tcb1)=r0;
/* Initialize SPORT DMA transfer by writing to the CP reg */
dm(CPSP1A)=r0;

_main.end:  jump (pc,0);