sport core driven.asm

来自「ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代」· 汇编 代码 · 共 101 行

/* SPORT Control Registers */
#define TXSP2A  0x460
#define RXSP3A  0x465
#define DIV2    0x402
#define DIV3    0x403
#define SPCTL2  0x400
#define SPCTL3  0x401
#define SPMCTL23 0x404

/* SPMCTL Bits */
#define SPL     0x00001000

/* SPCTL Bits */
#define SPEN_A  0x00000001
#define SDEN_A  0x00040000
#define SLEN32  0x000001F0
#define SPTRAN  0x02000000
#define IFS     0x00004000
#define FSR     0x00002000
#define ICLK    0x00000400

/* Default Buffer Length */
#define BUFSIZE 10

.SECTION/DM seg_dmda;
/* Transmit Buffer */
.var tx_buf2a[BUFSIZE]= 0x11111111,
                        0x22222222,
                        0x33333333,
                        0x44444444,
                        0x55555555,
                        0x66666666,
                        0x77777777,
                        0x88888888,
                        0x99999999,
                        0xAAAAAAAA;

/* Receive Buffer */
.var rx_buf3a[BUFSIZE];

/* Main code section */
.global _main;
.SECTION/PM seg_pmco;
_main:
//bit set mode1 CBUFEN;    /* enable circular buffers

/*//////////////////////////////////////////////////////////
//                                                        //
//  SPORT Loopback: Use SPORT2 as RX & SPORT3 as TX       //
//                                                        //
//////////////////////////////////////////////////////////*/

/* Initially clear SPORT control registers */
r0=0x00000000;
dm(SPCTL2)=r0;
dm(SPCTL3)=r0;
dm(SPMCTL23)=r0;

/* Set up DAG registers */
i4=tx_buf2a;
m4=1;
i12=rx_buf3a;
m12=1;

SPORT_DMA_setup:
/* set internal loopback bit for SPORT2 & SPORT3 */
bit set ustat3 SPL;
dm(SPMCTL23) = ustat3;

/* Configure SPORT2 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV=[fCCLK(200MHz)/2xFSCLK(20MHz)]-1 = 0x0004 */
/* FSDIV=[FSCLK(20 MHz)/TFS(.625 MHz)]-1 = 31 = 0x001F */
R0 = 0x001F0004;    dm(DIV2) = R0;
ustat4 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR|       /* Frame Sync Required */
         SPTRAN|    /* Transmit on enabled channels */
         IFS|       /* Internally Generated Frame Sync */
         ICLK;      /* Internally Generated Clock */
dm(SPCTL2) = ustat4;

/* Configure SPORT3 as a receiver */
/* externally generating clock and frame sync */
r0=0x0;     dm(DIV3) = R0;
ustat3 = SPEN_A|    /* Enable Channel A */
         SLEN32|    /* 32-bit word length */
         FSR;       /* Frame Sync Required */
dm(SPCTL3) = ustat3;

/* Set up loop to transmit and receive data */
lcntr = LENGTH(tx_buf2a), do (pc,_loop_end) until lce;
/* Retrieve data using DAG1 and send TX via SPORT2 */
r0=dm(i4,m4);
dm(TXSP2A)=r0;
/* Receive data via SPORT3 and save via DAG2 */
r0=dm(RXSP3A);
_loop_end: pm(i12,m12)=r0;

_main.end:  jump (pc,0);