programmable clock generator external input clock.asm

ADI 公司的DSP ADSP21262 EZ-KIT LITE开发板的全部源代码

/* Register Definitions */
#define SRU_CLK3    0x2434
#define SRU_PIN0    0x2460
#define SRU_PBEN0   0x2478
#define PCG_CTLA0   0x24C0
#define PCG_CTLA1   0x24C1
#define PCG_CTLB0   0x24C2
#define PCG_CTLB1   0x24C3
#define PCG_PW      0x24C4

/* SRU Definitions */
#define PCG_CLKA_O      0x1c
#define PCG_CLKB_P      0x39
#define PCG_FSB_P       0x3B
#define PBEN_HIGH_Of    0x01

//Bit Positions
#define PCG_EXTB_I      5
#define DAI_PB02        6
#define PCG_PWB         16

/* Bit Definitions */
#define ENCLKA      0x80000000
#define ENFSB       0x40000000
#define ENCLKB      0x80000000
#define CLKBSOURCE  0x80000000
#define FSBSOURCE   0x40000000

/* Main code section */
.global _main; /* Make main global to be accessed by ISR */
.section/pm seg_pmco;
_main:
/*Route PCG Channel A clock to PCG Channel B Input via SRU*/
r0=(PCG_CLKA_O<<PCG_EXTB_I);
dm(SRU_CLK3)=r0;

/* Route PCG Channel B clock to DAI Pin 1 via SRU */
/* Route PCG Channel B frame sync to DAI Pin 2 via SRU */
r0=(PCG_CLKB_P|(PCG_FSB_P<<DAI_PB02));
dm(SRU_PIN0)=r0;

/* Enable DAI Pins 1 & 2 as outputs */
r0=(PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02));
dm(SRU_PBEN0)=r0;

r0=ENCLKA; /* Enable PCG Channel A Clock, No Channel A FS */
           /* FS Divisor = 0, FS Phase 10-19 = 0 */
dm(PCG_CTLA0)=r0;

r1=0xfffff; /* Clk Divisor = 0xfffff, FS Phase 0-9 = 0 */
            /* Use CLKIN as clock source */
dm(PCG_CTLA1)=r1;

r0=(5<<PCG_PWB); /* PCG Channel B FS Pulse width = 1 */
dm(PCG_PW)=r0;

r0=(ENFSB|ENCLKB|10); /*Enable PCG Channel B Clock and FS*/
            /* FS Divisor = 10, FS Phase 10-19 = 0 */
dm(PCG_CTLB0)=r0;

r0=(CLKBSOURCE|FSBSOURCE|10); /* Clk Divisor = 10 */
     /* FS Phase 0-9 = 0, Use SRU_MISC4 as clock source */
dm(PCG_CTLB1)=r0;

_main.end: jump(pc,0);