📄 adi_ssl_init.c
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ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {
{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank_size },
{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width },
{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)cl_threshold },
{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN, (void*)&trasmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN, (void*)&trpmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN, (void*)&trcdmin },
{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN, (void*)&twrmin },
{ ADI_EBIU_CMD_SET_SDRAM_REFRESH, (void*)&refresh },
/* Asynch Commands memory controller commands */
{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },
{ ADI_EBIU_CMD_END, 0 }
};
#endif
/********************************************************************/
#if defined(__ADSP_TETON__) // BF561 EZKit
ADI_PWR_COMMAND_PAIR ezkit_power[] = {
{ ADI_PWR_CMD_SET_PROC_VARIANT, (void*)ADI_PWR_PROC_BF561SKBCZ500X }, // 500Mhz ADSP-BF561
{ ADI_PWR_CMD_SET_PACKAGE, (void*)ADI_PWR_PACKAGE_MBGA }, // in MBGA packaging, as on all EZ-KITS
{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 }, // external voltage supplied to the voltage regulator is 3.3V
{ ADI_PWR_CMD_SET_CLKIN, (void*)30 }, // the CLKIN frequency 30 MHz
#if defined( ADI_SSL_DUAL_CORE )
{ ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED, NULL }, // enable autosync so the core A and B sync up
#endif
{ ADI_PWR_CMD_END, 0 }
};
ADI_EBIU_TIMING_VALUE twrmin = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}}; // set min TWR to 1 SCLK cycle + 7.5ns
ADI_EBIU_TIMING_VALUE refresh = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}}; // set refresh period to 8192 cycles in 64ms
ADI_EBIU_TIME trasmin = {44, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRAS to 44ns
ADI_EBIU_TIME trpmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRP to 20ns
ADI_EBIU_TIME trcdmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRCD to 20ns
u32 cl_threshold = 100; // set cl threshold to 100 Mhz
// Teton has four separately configurable banks. Only one bank is used on the EZ-Kit
ADI_EBIU_SDRAM_BANK_VALUE bank0_size = {0, {size: ADI_EBIU_SDRAM_BANK_64MB }}; // set bank 0 size to 64MB
ADI_EBIU_SDRAM_BANK_VALUE bank0_width = {0, {width: ADI_EBIU_SDRAM_BANK_COL_10BIT}}; // set bank 0 column address width to 10-Bit
/* Set 16 bit packing enable for all four asynch banks */
ADI_EBIU_ASYNCH_BANK_VALUE asynch_bank_packing_enable = { ADI_EBIU_BANK_ALL, { data_path: ADI_EBIU_ASYNCH_BANK_DATA_PATH_16 }};
/* Teton uses bank 3 for Netchip device. Overwrite the global "bank_all" configuration of this bank */
/* time between Read Enable assertion to de-assertion */
ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank3_read_access_time = { ADI_EBIU_BANK_3, { 3, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
/* time between Write Enable assertion to de-assertion */
ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank3_write_access_time = { ADI_EBIU_BANK_3, { 1, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
/* time from beginning of memory cycle to R/W-enable */
ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank3_setup_time = { ADI_EBIU_BANK_3, { 1, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
/* time from de-assertion to end of memory cycle */
ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank3_hold_time = {ADI_EBIU_BANK_3, { 3, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {
{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank0_size },
{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank0_width },
{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)cl_threshold },
{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN, (void*)&trasmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN, (void*)&trpmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN, (void*)&trcdmin },
{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN, (void*)&twrmin },
{ ADI_EBIU_CMD_SET_SDRAM_REFRESH, (void*)&refresh },
/* Asynch Commands memory controller commands */
{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },
/* Teton uses bank 3 for the Netchip device so send these additional commands*/
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank3_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank3_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank3_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank3_hold_time },
{ ADI_EBIU_CMD_END, 0 }
};
#endif
/********************************************************************/
#if defined(__ADSP_STIRLING__) // BF538 EZKit
ADI_PWR_COMMAND_PAIR ezkit_power[] = {
{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF538BBCZ500 }, // 500Mhz ADSP-BF538
{ ADI_PWR_CMD_SET_PACKAGE, (void*)ADI_PWR_PACKAGE_MBGA }, // in MBGA packaging, as on all EZ-KITS
{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 }, // external voltage supplied to the voltage regulator is 3.3V
{ ADI_PWR_CMD_SET_CLKIN, (void*)25 }, // the CLKIN frequency 25 MHz
{ ADI_PWR_CMD_END, 0 }
};
ADI_EBIU_TIMING_VALUE twrmin = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}}; // set min TWR to 1 SCLK cycle + 7.5ns
ADI_EBIU_TIMING_VALUE refresh = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}}; // set refresh period to 8192 cycles in 64ms
ADI_EBIU_TIME trasmin = {44, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRAS to 44ns
ADI_EBIU_TIME trpmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRP to 20ns
ADI_EBIU_TIME trcdmin = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; // set min TRCD to 20ns
u32 cl_threshold = 100; // set cl threshold to 100 Mhz
ADI_EBIU_SDRAM_BANK_VALUE bank_size = {0, {size: ADI_EBIU_SDRAM_BANK_64MB }}; // set bank size to 64MB
ADI_EBIU_SDRAM_BANK_VALUE bank_width = {0, {width: ADI_EBIU_SDRAM_BANK_COL_10BIT}}; // set column address width to 10-Bit
ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {
{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE, (void*)&bank_size },
{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width },
{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD, (void*)cl_threshold },
{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN, (void*)&trasmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN, (void*)&trpmin },
{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN, (void*)&trcdmin },
{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN, (void*)&twrmin },
{ ADI_EBIU_CMD_SET_SDRAM_REFRESH, (void*)&refresh },
/* Asynch Commands memory controller commands */
{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },
{ ADI_EBIU_CMD_END, 0 }
};
#endif
/*******************************************************************************/
#if defined(__ADSP_MOAB__) /* BF548 EZKit */
ADI_PWR_COMMAND_PAIR ezkit_power[] = {
{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF548SBBC1533 }, /* 533Mhz ADSP-BF548 */
{ ADI_PWR_CMD_SET_PACKAGE, (void*)ADI_PWR_PACKAGE_MBGA }, /* in MBGA packaging, as on all EZ-KITS */
{ ADI_PWR_CMD_SET_VDDEXT, (void*)ADI_PWR_VDDEXT_330 }, /* external voltage supplied to the voltage regulator is 3.3V */
{ ADI_PWR_CMD_SET_CLKIN, (void*)25 }, /* the CLKIN frequency 25 MHz */
{ ADI_PWR_CMD_END, 0 } /* indicates end of table */
};
ADI_EBIU_TIMING_VALUE RC = { 8, {60, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles between one active command and the next */
ADI_EBIU_TIMING_VALUE RAS = { 6, {42, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles between active command and precharge command */
ADI_EBIU_TIMING_VALUE RP = { 2, {15, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles between precharge command and active command */
ADI_EBIU_TIMING_VALUE RFC = { 10,{72, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles for SDRAM to recover from REFRESH signal */
ADI_EBIU_TIMING_VALUE WTR = { 1, {7500,ADI_EBIU_TIMING_UNIT_PICOSEC }}; /* cycles from last write data until next read command */
ADI_EBIU_TIMING_VALUE tWR = { 2, {15, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* write recovery time is 2 or 3 cycles */
ADI_EBIU_TIMING_VALUE tMRD = { 2, {15, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles from setting of mode */
ADI_EBIU_TIMING_VALUE RCD = { 2, {15, ADI_EBIU_TIMING_UNIT_NANOSEC }}; /* cycles from active command to next R/W */
ADI_EBIU_TIMING_VALUE REFI = { 1037,{7777, ADI_EBIU_TIMING_UNIT_NANOSEC}}; /* cycles from one REFRESH signal to the next */
ADI_EBIU_COMMAND_PAIR ezkit_ram[] = {
{ ADI_EBIU_CMD_SET_DDR_REFI, (void*)&REFI }, /* command to set refresh interval */
{ ADI_EBIU_CMD_SET_DDR_RFC, (void*)&RFC }, /* command to set auto refresh period */
{ ADI_EBIU_CMD_SET_DDR_RP, (void*)&RP }, /* command to set precharge to active time */
{ ADI_EBIU_CMD_SET_DDR_RAS, (void*)&RAS }, /* command to set active to precharge time */
{ ADI_EBIU_CMD_SET_DDR_RC, (void*)&RC }, /* command to set active to active time */
{ ADI_EBIU_CMD_SET_DDR_WTR, (void*)&WTR }, /* command to set write to read time */
{ ADI_EBIU_CMD_SET_DDR_DEVICE_SIZE, (void*)0 }, /* command to set size of device */
{ ADI_EBIU_CMD_SET_DDR_CAS, (void*)2 }, /* command to set cycles from assertion of R/W until first valid data */
{ ADI_EBIU_CMD_SET_DDR_DEVICE_WIDTH, (void*)2 }, /* command to set width of device */
{ ADI_EBIU_CMD_SET_DDR_EXTERNAL_BANKS,(void*)0 }, /* command to set number of external banks */
{ ADI_EBIU_CMD_SET_DDR_DATA_WIDTH, (void*)0 }, /* command to set data width */
{ ADI_EBIU_CMD_SET_DDR_WR, (void*)&tWR }, /* command to set write recovery time */
{ ADI_EBIU_CMD_SET_DDR_MRD, (void*)&tMRD }, /* command to set cycles from setting mode reg until next command */
{ ADI_EBIU_CMD_SET_DDR_RCD, (void*)&RCD }, /* command to set cycles from active command to a read/write assertion */
/* Asynch Commands memory controller commands */
{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE, (void*)&clkout_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE, (void*)&banks_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME, (void*)&asynch_bank_trans_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME, (void*)&asynch_bank_read_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME, (void*)&asynch_bank_setup_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME, (void*)&asynch_bank_hold_time },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE, (void*)&asynch_bank_ardy_enable },
{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY, (void*)&asynch_bank_ardy_polarity },
{ ADI_EBIU_CMD_END, 0 } /* indicate the last command of the table */
};
#endif
/********************************************************************/
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