exceptions.s

mpc564 时钟中断 时钟中断

	.name "exceptions.s" 
								      	 
	.section .abs.00000100		
		b _start		; System reset exception, per crt0 file

	.section .abs.00000500		
		b external_interrupt_exception

	.text
external_interrupt_exception:

	.equ	SIVEC, 		0x2fc01c	;Register addresses   

						; STEP 1:  SAVE "MACHINE CONTEXT"
	stwu	sp, -80 (sp); Create stack frame and store back chain
	stw		r3, 36 (sp)	; Save working register
	mfsrr0	r3			; Get SRR0
	stw		r3, 12 (sp)	; and save SRR0
	mfsrr1	r3			; Get SRR1
	stw		r3, 16 (sp)	; and save SRR1


						; STEP 2:  MAKE MSR[RI] RECOVERABLE
	mtspr	EID, r3		; Set recoverable bit
						; Now debugger breakpoints can be set


						; STEP 3: SAVE OTHER APPROPRIATE CONTEXT
	mflr	r3			; Get LR
	stw		r3, 8 (sp)	; and save LR
	mfxer	r3			; Get XER
	stw		r3, 20 (sp)	; and save XER
	mfspr	r3, CTR		; Get CTR
	stw		r3, 24 (sp)	; and save CTR
	mfcr	r3			; Get CR
	stw		r3, 28 (sp)	; and save CR
	stw		r0, 32 (sp)	; Save R0
	stw		r4, 40 (sp)	; Save R4 to R12
	stw		r5, 44 (sp)
	stw		r6, 48 (sp)
	stw		r7, 52 (sp)	
	stw		r8, 56 (sp)	
	stw		r9, 60 (sp)	
	stw		r10, 64 (sp)
	stw		r11, 68 (sp) 
	stw		r12, 72 (sp)

						; STEP 4: DETERMINE INTERRUPT SOURCE
	lis		r3, SIVEC@ha 	; Load higher 16 bits of SIVEC address
	lbz		r3, SIVEC@l (r3) ; Load Interrupt Code byte from SIVEC
						; Interrupt Code will be jump table	index

	lis		r4, IRQ_table@h ; Load interrupt jump table base address
	ori		r4, r4, IRQ_table@l 
	add		r4, r3, r4		; Add index to table base address
	mtlr	r4			; Load result address to link register


						; STEP 5: BRANCH TO INTERRUPT HANDLER
	blrl				; Jump to Execution Routine (subroutine)
						; (After returning here, restore context)


						; STEP 6: RESTORE CONTEXT
	lwz		r0, 32 (sp)	; Restore gprs except R3 
	lwz	 	r4, 40 (sp)	
	lwz	 	r5, 44 (sp)
	lwz		r6, 48 (sp)
	lwz		r7, 52 (sp)
	lwz		r8, 56 (sp)
	lwz		r9, 60 (sp)
	lwz		r10, 64 (sp)
	lwz		r11, 68 (sp)
	lwz		r12, 72 (sp)
	lwz		r3, 20 (sp)	; Get XER
	mtxer	r3			; and restore XER
	lwz		r3, 24 (sp)	; Get CTR
	mtctr	r3			; and restore CTR
	lwz		r3, 28 (sp)	; Get CR
	mtcrf	0xff, r3	; and restore CR
	lwz		r3, 8 (sp)	; Get LR
	mtlr	r3			; and restore LR
	mtspr	NRI, r3		; Clear recoverable bit, MSR[RI]
						; Note: breakpoints CANNOT be set
						; from now thru the rfi instruction
	lwz		r3, 12 (sp)	; Get SRR0 from stack
	mtsrr0	r3			; and restore SRR0
	lwz		r3, 16 (sp)	; Get SRR1 from stack
	mtsrr1	r3			; and restore SRR1
	lwz		r3, 36 (sp)	; Restore R3
	addi	sp, sp, 80	; Clean up stack


						; STEP 7:  Return to Program 
	rfi					; End of Interrupt

; ===================================================================
; Branch table	for the different SIVEC Interrupt Code values:

IRQ_table:		   		; Branch forever if routine is not written

irq_0:		b	irq_0
level_0:	b	level_0
irq_1:		b	irq_1
level_1:	b	level_1
irq_2:		b	irq_2
level_2:	b	level_2
irq_3:		b	irq_3
level_3:	b	level_3		
irq_4:		b	irq_4
level_4:	b	level_4
irq_5:		b	irq_5
			b	SCI_Int	; Branch to SCI C routine
irq_6:		b	irq_6
level_6:	b	level_6
irq_7:		b	irq_7
level_7:	b	level_7